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Hi,
In Mealy machine, the output depends both on the current state and the input. hence it can change with change in any of these thus has the probability of generating a glitch. whereas in moore machine output depends only on the current state i. e output changes with change in state only (synchronized with the clock) hence the glitch is not present in moore.
hope this is clear
A Moore state machine is more
efficient than a Mealy state machine -
Because of Moore state machine has synchronous outputs
– no glitches
– one cycle “delay”
– full cycle of stable output
And Mealy machine has asynchronous outputs
– if input glitches, so does output
– output immediately available
– output may not be stable long
enough to be useful -> If output of Mealy FSM
goes through combinational logic before being
registered, the CL might delay the signal and it could
be missed by the clock edge.
When I was a student at Imperial College London, the followings are taught by Professor Cheung C Y. I hope the following pointers are helpful to many who might not fully understood FSMs.
1. Output from a Moore Machine is always valid throughout the entire cycle, EXCEPT during transition.
2. Output from a Mealy Machine is ONLY valid immediately after a transition.
3. Both Moore and Mealy has a control logic that captures the input. Should the input change due to glitches, at the same time when the state register just produced the next state to the control logic, it will affect both Moore and Mealy. Since Mealy has its output logic that captures the input, glitches will affect Mealy.
4. Latched Mealy is used to resolved output contention problem in high-speed synchronous digital system. Not to resolve glitches.
Again, agree with funster that both are safe if setup/hold req are met.
Conversely, both are unsafe if setup/hold are not met.
Remember that there is a piece of combinational logic after the state flip-flops to produce the outputs, in both Moore and Mealy. This logic may glitch, unless you design it to be hazard free.
glitches in the input r not propagated to the output.
Added after 4 minutes:
see, in moore, the input to the output is the output of the flop, which settles after clock to q delay and does NOT change thereafter for the entire clock cycle but if the o/p of ur fsm is dependent on inpt(which can change ANYTIME), then the o/p of ur fsm too can change ANYTIME.
C'mon nobody uses Mealy in the industry. It is only used in colleges for students to learn this novel FSM. In fact Moore is also very much confined to colleges because it is easier to determine the a sequential system using Moore.
In the industry, latched Mealy or Mealy with a registered output is used. Just that the output only appears in the next state, very much like Moore.
As I have already said,
1. Output from a Moore Machine is always valid throughout the entire cycle, EXCEPT during transition.
2. Output from a Mealy Machine is ONLY valid immediately after a transition.
Glitches at the input, IF violated the setup time, WILL be propagated to the output as well, in a Mealy Machine.
There is nothing to disagree. This is a technical fact, stated black and white in Wakerly's book, Randy Katz's book, Michael Smith's book,, Ashenden' book and I believe many more books on Digital System Design, VHDL, or Sequential Machines etc.
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