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100MHz SPI Clokck Generation

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reservevoltage

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Hi there,

I have a trouble with spı clock. Please consider that ı like a toddler for logic circuits.

SCKI frequency has an oscillation when ı tried to create 100MHz PWM clock for SCKI. My reference clock is generated by 100MHz sinus active osilator.

Actully, Simulation is ok. oscillation wasnt occured.

However when the code is runned at EPM570T100C5N or EPM240T100C5N, oscillation occurs.

Also ı tried to create 25MHz and 50Mhz PWM from 100MHz sinus but faced oscillation again.

I wonder that do ı have to change the referance clock signal from sinus to PWM or code approch?
 

Hi,

A lot of confusion.

100MHz SPI clock? I never heared about that high SPI clock frequency. But surely possible. What devices do you want to communicate with each other?

Please consider that ı like a toddler for logic circuits.
Click to expand...
What does this mean?

PWM:
Means: Pulse Width Modulation. Surely an SPI clock does not want pulse width to be modulated.

My reference clock is generated by 100MHz sinus active osilator.
Click to expand...
Please confirm that the PLDs can work with sinusoidal clock frequency.
Please confirm that the logic inside your PLDs can work with 100MHz at all.

You talk about code....Where is it?
--> Show your code.

Also show your schematic and your simulation.

Klaus
 

Hi KlausST,

ı have tried to communicate between ltc2335-16 and EPM240t100c5.

Means: Pulse Width Modulation. Surely an SPI clock does not want pulse width to be modulated.
Click to expand...

ı wanted to indicate SCKI signal and have a demoboard which name is cpld c-m240

ı couldnt share a real code unfortunatelly because of remote location.

A shared code is a part of real code.

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
    
entity main is
  generic(
    N : integer := 16
  );
  Port ( 
    in_clk : in std_logic;
    in_rst : in std_logic;
    out_clk_2 : out std_logic;
    out_clk_4 : out std_logic;
    out_clk_8 : out std_logic;
    out_clk_16 : out std_logic;
    out_clk_N : out std_logic                                                     
  );
end main;
    
architecture Behavioral of main is
  signal r_sayac : std_logic_vector(3 downto 0) := (others => '0');
  signal r_sayac_N : integer := 0;
begin
    
  out_clk_2  <= r_sayac(0);
  out_clk_4  <= r_sayac(1);
  out_clk_8  <= r_sayac(2);
  out_clk_16 <= r_sayac(3);
  out_clk_N  <= '0' when r_sayac_N < N / 2 else '1';
    
  process(in_clk, in_rst)
  begin
    if in_rst = '1' then
      r_sayac <= (others => '0');
      r_sayac_N <= 0;
    
    elsif rising_edge(in_clk) then
      r_sayac <= r_sayac + 1;        
      if r_sayac_N = N - 1 then
        r_sayac_N <= 0;
      else   
        r_sayac_N <= r_sayac_N + 1;
      end if;                   
    end if;
  end process;
end Behavioral;


scope pictures are attached.

referance clock.JPG

IMG_3450.JPG

IMG_3448.JPG

IMG_3450.JPG
 
Last edited by a moderator:

You are using incorrect terminology in your posts, so your questions don't make any sense.

What you have shown for your VHDL code is a simple divide by 2, 4, 8, and 16, with another divide by N/2 output.

Your scope traces have no information on what they represent so are useless. Not knowing what they mean all I can say is that you are probably not using the scope correctly as all the signals you have shown look like they are missing a ground lead as they all have severe overshoot, undershoot, and ringing.

Other than that observation I can't comment on any of your questions as I don't understand what you are even asking.
 

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