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How to verify asynchronous FIFO RAM

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Re: q of verification?

1) Create verification plan
2) Create testbench, using HDL or e.
3) Create testcases.
4) Run simulation.
5) Check results and coverage.

Regards,
 

q of verification?

don't know how. the asynchronous FIFO ram is very difficult to verify.
 

q of verification?

1) write a plan: what conditions to be verified.
for example: only read; only write; A read B write and A faster than B; A read B write and B faster than A; A write B read A faster than B;...
2) build verification enviorenment for such plan.
3) analysis, and FPGA board verification to find more corener conditions that you haven't thought of, and add them into the plan in (1), complement the verification enviorenment by adding more patterns.
 

Re: q of verification?

1. FIFO full
2. FIFO empty
3. FIFO overflow
4. FIFO underflow
5. Reset recovery (If FIFO can be given soft reset). Also during reset nothing should be written and occupancy should
remain zero. Also during reset nothing should be read out of FIFO and occupancy should remain zero.
6. Simultaneous read and write when FIFO is empty, FULL, half full, one entry in FIFO, one entry less than FULL.
7. If FIFO has near FULL and NEAR empty then validate that also.
8. Check following combinations - WWWW, WRWRWR, RRRR, WWRRWWRR, WWRWWR, RRWRRW.
 

Re: q of verification?

FIFO ram usually is dual port ram generated by memory compiler.
memory compiler give a verilog model. the controller written by youself verify flag of empty, full , half empty and half empty (if need) with ram model .
 

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