What does "unsynthesizable vhdl code" mean?

hi there,i'm a beginner in vhdl, can someone explain to me what "unsynthesizable vhdl code" means ?

unsynthesizable constructs vhdl

unsynthesizable VHDL means VHDL code that contains constructs, statements
that cannot be synthesized or the statments that has no equivalent for hardware
in the SYNTHESIS TOOL,

u can refer various BOOKS for VHDL, SYNTHESIS tool MANUAL for reference

unsynthesizable code

Unsynthesizeable VHDL code is used just for simulation, this code can not be synthesized.
If you design for synthesis is different.

how to avoid vhdl code that cannot be synthesized

Do I have to study everything about VHDL,or should I only study the parts that can be synthesized?

unsynthesizable

cmos babe said:

Do I have to study everything about VHDL,or should I only study the parts that can be synthesized?

Click to expand...

when u learn synthesizable VHDL... u already will know wad is unsynthesizable along the learning process.... i dont think there is a course where u only learn bout unsynthesizable vhdl code...tht is no usefulness in it...

regards,
sp

synthesizable versus unsynthesizable

Well there are some books that make difference between VHDL for synthesis and VHDL for simulation (unsynthesizable).

unsynthesizable constructs in vhdl

you do require some knowledge of unsynthesizable codes for verification purposes... any vhdl book as such doesnt separate out the synthesizable code and concentrate on them.. you need to have a knowledge of both.

unsynthesizable constructs in vhdl

U can refer to VHDL synthesis primer by bahsakr (not sure of the author name spelling) as a good tutorial or the hdl synthesis manual in the help of leonardo spectra.
The synthesiable VHDL is used for describing the actual circuit.
The unsynthesiable VHDL is used only for testbenches although it can be written using synthesiable VHDL constructs.
P.S: There is an IEEE puplication illustrating the synthesiable constructs.

un-synthesizable code

There is a mistake that many people do when begining to program for FPGA, especially if those people previously programmed structured language like 'C'.

You have to think, throughout your design, that you're implementing hardware functions, and not a sequential program. You have to keep in mind that everything happen in parallel. For example, you can not synthesize a for loop. A for loop is a sequential thing. This is good for simulating (testbenching) only. So, to design something that work like a for loop, you have to synthesize a counter, and do different things depending on the output. The counter become one entity, and the actions (logic blocks) depending on the counter output is another entity.

Can you post an example of what's not synthesizable?

hardware unsynthesizable coe

u must make a code synthesizable and also simulatable.

to ensure this avoid functions and procedures as possible, use std_logic type as long as its possible, use signals instead of variables as u can.

for example input of type U(uninitialized) or Z(high impedance),or X(unknown) is impossible in any real circuit so this code is not synthesizable(inputs are either logic 1 or 0)

things which cant happen in real will be unsynthesizable.

unsynthesizable VHDL

If you dont restrict yourself to using the synthesisale subset of vhdl the code become non sysnthesisable , The behaviour models are also in need for simuation , architecture purpose

Re: unsynthesizable VHDL

hi..
unsynthesizable means something that cannot be realized with gates. Here the behaviour of the code may be correct but u may not able to realize a hardware that can perform the same functionality.
Ex. declairing a clock'event inside another Clk'event is unsynthesizable. Just for the fact that u cannot detect both these edges at the same time one after the other. For writing a synthesizable VHDL code u must think first of all that whatever u r writing can be really b done in hardware. Think first of all that u can realize a hardware 4 that then only ur synthesis tool will be able to do.
The other thing is practice and exoerience. As u do more n more programming and synthesize ur designs, u will come accross a lot of constructs that r simulatable but not synthesizable. So try learn and make more n more programs. Thas It.

Check out this attached file. This file is REALLY GOOD.....

Re: unsynthesizable VHDL

Hi,

Synthesizable VHDL code use only subset of VHDL laguage.

You can use VHDL for logic synthesys, high-level functional description and for simulation (test vector generation and verification).

To produce synthesizable VHDL code you must use only syntesizable VHDL instructions.