Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Simple concurrent statement written for fpga, value doesn't change.

Status
Not open for further replies.
R

Ruddwijk

Newbie level 1
Joined
Mar 2, 2017
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
8
So, i have a fairly simple code written with concurrent statements. However, when testing, LdBuf gives "0000000000000001" and then doesn't change with D_Add. Have i missed something? Not experienced in writing concurrent code, or using others.

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity DestinationDecoder is
    Port ( W: in  STD_LOGIC;
           D_Add: in  STD_LOGIC_VECTOR (3 downto 0);
           Ld: out  STD_LOGIC_VECTOR (15 downto 0));
end DestinationDecoder;

architecture Behavioral of DestinationDecoder is
signal LdBuf: std_logic_vector(15 downto 0):= (others => '0');
begin

LdBuf <= (to_integer(unsigned(D_Add(3 downto 0))) => '1', others => '0');
Ld <= "0000000000000000" when (W = '0') else
	LdBuf;

end Behavioral;
 

Sorry - misread code originally.

Check that the RTL diagram actually has the hardware you think. I know quartus has had bugs in the past with this type of code.

- - - Updated - - -

try this code instead, it is functionally identical:

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10

process(D_Add)
begin
  LdBuf <= (others => '0');
 
  for i in LdBuf'range loop
    if unsigned(D_Add) = i then 
      LdBuf(i) <= '1'
    end if;
  end loop;
end process;
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top