What is delay in the DFE implementation?

Hello,

I know Decision Feedback Equalizer when I did research in university. Now I am interested in its ASIC chip implementation. This paper is interesting on its DFE implementation.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010
Page 909
A 21-Gb/s 87-mW Transceiver
With FFE/DFE/Analog Equalizer
in 65-nm CMOS Technology
Huaide Wang and Jri Lee, Member, IEEE

It said:
To accelerate the feedback, we merge the adder and the
slicer into the flipflop as shown in Fig. 18. Now, the output
directly feeds back to the input with a coefficient , which is
implemented in current mode. The pair thus M11-M12 carries
the feedback signal. It is equivalent to dynamically adjust the
threshold level of the sampler based on the previous result. That
is, if the previous bit is “0”, the current bit will be considered
“1” if the output crosses V_l, and vice versa.

As I know, the output of DFE has to be delayed when it is added with the input signal.
But I don't see it in Fig.18 below. Fig.17 showed a FF as the delay component. Where is it in Fig. 18?

Thanks,