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Given that this is a rotate right and a is probably supposed to be implemented as flip-flops, you shoul probably be using a non-blocking assignment (<=) instead of a blocking assignment (=).
a is a bus of 8-bits. a[7:0] can be referred to as a only. Assigning something to a will assign each bit fom LSB to MSB until you run out of bits to assign or you run out of bits that ca be assigned (i.e. Verilog perfoms zero fill or truncation respectively). The {} operation make whatever signals in between the braces a new bus that is made up of the items between the braces.
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