CMOS Technology selection?

Hi guys,

I am in a stage to decide which technology should I use for my IC that I want to fabricate. Our lab is new and it is the first IC we intended to fabricate. would you please share your advise on how we select the fabrication technology? we are targeting to Fabricate using TSMC technologies provided by MOSIS.

the circuit is mixed with analog and digital, CMOS is targeted. our high priority is the cost of Fabrication and timing schedule flexibility of fabrication.

cost? then go with 65nm. still, be prepared to spend ~50k on a MPW.

Cost means different things to different people.

Per-die in the billions? TSMC or similar, at a couple of nodes
back from the leading edge (unless you need leading edge
density, quite unlikely for a sensors experiment).

Budget in the tens of $K? Has to be a multiproject run.
You can find many resources there in and out of MOSIS,
for example TowerJazz and OnSemi both host similar
activities internally, I expect others I'm unaware of.
Some price by area, some offer only a fixed size tile,
this is another cost dimension.

You need to think about your design's component
attributes - at 65nm TSMC, probably some 0.9V-ish
logic devices, some 2.5V I/O devices and not much
else - is that good, or do you want something much
older like a 0.35u mixed signal CMOS that can run
off a lithium cell without a pair of regulators off-
chip, maybe has high quality passives? Maybe this
matters not much to an experiment but could be a
big deal, path-to-product-wise.

Probably attack it from both ends (cost, capabilities)
and see who (if anyone) is left standing in the middle.

ThisIsNotSam said:

cost? then go with 65nm. still, be prepared to spend ~50k on a MPW.

Click to expand...

would you elaborate what do you mean by MPW?

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dick_freebird said:

Cost means different things to different people.
you need to think about your design's component
attributes - at 65nm TSMC, probably some 0.9V-ish
logic devices, some 2.5V I/O devices and not much
else - is that good, or do you want something much
older like a 0.35u mixed signal CMOS that can run
off a lithium cell without a pair of regulators off-
chip, maybe has high quality passives? Maybe this
matters not much to an experiment but could be a
big deal, path-to-product-wise.

Probably attack it from both ends (cost, capabilities)
and see who (if anyone) is left standing in the middle.

Click to expand...

Thanks man, I like your points. definitely will look at them and try to see good option.

I have a question, sorry it is maybe basic, what do you mean by 0.9V, 2.5V or 3.3 I/O devices? it this the highest voltage can these devices handle, i.e. break-down voltage?
for example, in my case, I am expecting the stress for the switches around 1.8V max.

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maybe continuation to the question, how much differences are there between these technologies? for example, if I used 0.18um and then want to switch to 0.35um, will there few tweeks to have my circuit operational, or I need to redesign everything?

Oh dear, OP is lost.

MPW stands for multiproject wafer. It's the only way you will buy semi-affordable silicon. MOSIS puts your chips next to someone else's and saves money for the both of you. The mask cost is shared.

I/O devices are for chip I/Os, not for the core. It's the voltage to which you will interface with the external world. The process choice limits what voltages you can get, and values like 1.8, 2.5, and 3.3 are pretty common. If you have a strong preference for any I/O voltage, you will have to find a process that supports what you need. It means nothing to the transistors in your chip core area, as they will still operate at ~1V. And they will breakdown at [1.6-1.8] more or less.

switching to a different technology means almost complete rework.

You can use "I/O" devices in the "core". Used as actual I/O
there's more baggage; guardrings for latchup protection,
S/D silicide blocked regions for ESD current ballasting, etc.
But the thicker oxide devices, in the DGO (dual gate oxide
{thickness} flows I've used, are available also as plain FETs
that don't have to meet those style-rules.

TowerJazz CA18, which I have taped out on (on in-house
MPRs no less) has over a dozen variants. All about a core
1.8V device, but choice of 3.3V or 5V I/O (thicker gate)
devices, JI or SOI, 4 or 6 metal levels, MIM cap or not,
higher voltage devices on all but the SOI. MPR here being
"multiproject run" which is a short boat of multiproject wafers.
You will get sawn dice from one (or more) of N saw plans
that in sum provide whole dice for every customer (but, if
nonhomogeneous die dimensions, somebody takes it across
the gut on one plan, somebody else on another, like).
If you needed a wafer for some reason like postprocessing,
that's a tricky IP-leakage situation. Sensors people often
like that kind of thing, so be clear about your post-foundry
plans and what form you need. MOSIS will operate under
the same constraints, dice only.

ONC18, which I have also taped out on, I only know the
1.8/3.3 version but again there are some variants. Not
sure about I/O voltage but some "power management"
devices, multiple MIM cap density options etc.

Foundry PDK support also matters. If you're using Cadence
tools you've got a pretty free hand, everybody supports
them (you may face a Caliber golden verification suite, and
this can be a pain, a non-Cadence tool which may have a
discrepancy or three against the Cadence PDK implementation.
Being a small shop, I use Silvaco tools and have to use the
foundry's "mock tapeout" procedure to get a run done by
them, pull back the report and review at my end (the DRC
tools I have, fortunately can import the error report though
not execute the rules deck). The further afield you go in
tools, the worse the "seams" are and the worse your odds
of finding foundry-supplied PDKs to work in. Add this to the
list of questions to be asked up front.

Now one last (for now) thought. If you're a bioelectronics
guy at a university, check what the EECS department may
have going on with certain foundries and tools vendors.
Many universities with semiconductor sub-curricula have
periodic multiproject runs budgeted (if not for undergrads,
certainly for graduate classes and postdoc research).
If so, there's a finite chance that a bit of space might be
finagled out of professorial courtesy, interdepartmental
funds or keg bribes.