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Timing diagram for write and read transaction in AXI4

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sarit8

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Where can I find a timing diagram for write and read transaction in AXI4 (Including write channel response)?
 

Lol:) I have already dine it, but have not suceeded to find something with good explenation yet.
Click to expand...

Refer to the spec : ARM IHI 0022E (ID022613) which is also free to download.
There in you'll find the explanations and diagrams.
 

dpaul said:
Refer to the spec : ARM IHI 0022E (ID022613) which is also free to download.
There in you'll find the explanations and diagrams.
Click to expand...

I have aleady read it. There are just 2 basic diagarm (general transaction), and one more for barrier ntransaction,
 

the axi spec has descriptions of the signals and some of the guiding principles. The main ones:
1.) the master must advertise available data without waiting for the slave to become ready. This is repeated often.
2.) each channel can be acknowledged independently, even if this is annoying.
 

vGoodtimes said:
the axi spec has descriptions of the signals and some of the guiding principles. The main ones:
1.) the master must advertise available data without waiting for the slave to become ready. This is repeated often.
2.) each channel can be acknowledged independently, even if this is annoying.
Click to expand...

I have to find a diagram with all of the signals like AWSIZE, AWLEN, ASTRB WLAST etc.
 

I have to find a diagram with all of the signals like AWSIZE, AWLEN, ASTRB WLAST etc.
Click to expand...

Here you will find some simulation SS portraying AXI signals.
https://silica.avnet.com/wps/wcm/co...ev1.pdf?MOD=AJPERES&CVID=liIcQoZ&CVID=liIcQoZ

There isn't much out there other than from ARM. Engineers generally refer directly to the AMBA specs, understand them and then do their job. If you want details in a waveform diagram, grab a pencil and paper after you have understood the spec and get to work.
 


Re: AXI4- samplinf of WRADDR and WDATA

TrickyDicky said:
Becuase this allows back to back transactions.
A trasaction is accepted whenever WVALID and WRDY are high together.
Click to expand...


Yes but why? how?
How can we can send the data before the protocol "knows" the address?
 

Re: AXI4- samplinf of WRADDR and WDATA

sarit8 said:
Yes but why? how?
How can we can send the data before the protocol "knows" the address?
Click to expand...

It knows the address in parrallel with the data. So it connects the address to the address bus on the ram, and the data to the data bus.
This is hardware, not software.
 

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