Generating 150MHz external clock for ml605

Dear all,
I need to provide a 150MHz differential clock signal for MGTREFCLK on ml605 board.
I suppose I should use SMA MGT_CLK connector; but as far as I know, this clock should be provided externally. The problem is that ml605 differential clock generator frequency is at 200MHz.
a) How can I generate an external 150MHz differential clock signal?
b) There are two SMA user clock connectors on the board. Are these what I'm searching for? How do they work?
I'm somehow a newbie. I was wondering if you could help me.
Thanks.

a) How can I generate an external 150MHz differential clock signal?

Click to expand...

For sure this has to be done off chip.

b) There are two SMA user clock connectors on the board. Are these what I'm searching for? How do they work?

Click to expand...

I think so, I don't use the ML605.
Right now I am looking into the ug534.pdf, and as per Pg.31, I think SMA is the only option.
SMA Connectors (Differential)
A high-precision clock signal can be provided to the FPGA using differential clock signals
through the onboard 50Ω SMA connectors J58(P)/J55(N). This differential user clock has
the signal names USER_SMA_CLOCK_N and USER_SMA_CLOCK_P.

Thank you for your reply. I think I was not clear enough.
I need this signal for GTX (MGT) Clock, because I'm using SMA_RX_N, SMA_RX_P, SMA_TX_N, SMA_TX_P on X0Y18 MGT and I think I should use GTX SMA Clock; signals named SMA_REFCLK_N and SMA_REFCLK_P (On page 32 of ug534.pdf) not USER_SMA_CLOCK_N and USER_SMA_CLOCK_P. Am I wrong?(I tried that in .ucf file and it was OK)

I have already tried to connect the clock signal to SMA Connectors (The ones with USER_SMA_CLOCK_N and USER_SMA_CLOCK_P signals) in .ucf file but there were errors in mapping in ISE Design.
I also tried to use the Differential Oscillator mentioned on page 29 that produce 200 MHz clock signal and then used a mcm
to turn it to 150 MHz, but there were mapping errors again.
I prefer not to use external clock, is there a way to use internal clock or the clock oscillator on ml605 to produce a 150MHz clock signal for GTX(MGT)?

What was the error in MAP? Both methods should work, but there might be internal connections that need to be different for each. Likewise, there could be UCF or project issues -- things like declaring an incorrect device or incorrect pads.

According to GTX user manual, you need to connect an external reference clock source (as with other vendors Gbit transceiver blocks). So it's unlikely that the tools would you allow to connect an internally generated PLL clock. It may be possible to cheat the tool by feeding a PLL clock to a clock output and connect it externally to the refclk input, but probably the signal quality (e.g. jitter) will be unsuitable.

There are two same errors:

Place:1073 - Placer was unable to create RPM[BUFDS_RPMs] for the component
q4_clk1_refclk_ibufds_i of type BUFDS for the following reason.
The reason for this issue:
Some of the logic associated with this structure is locked. This should cause
the rest of the logic to be locked. A problem was found where we should
place BUFDS q4_clk1_refclk_ibufds_i off the edge of the chip in order to
satisfy the relative placement requirement of this logic. The following
components are part of this structure:

The MGTREFCLK to the GTX must have low phase noise. If the board has a high quality 200 MHz clock, your best option is to use it.
Are you sure you need 150 MHz?

- - - Updated - - -

I have now looked at the ML605 documentation. Which GTX are you using?
The SMA clock goes to bank 116, where also 125 MHz is available internally.
The GTX is quite flexible with the clock generation, so first check carefully if 125 MHz or 200 MHz can be used for your project.
If not, you must use an external clock generator or replace the 200 Mhz on-board oscillator.

do you have the project configured for the correct fpga, and all loc constraints set correctly?

The error sounds like you are trying to connect to a GTX tile that the tools think you don't have on your FPGA. In the past, I've also had issues with GTX placement and how the tiles are ordered. For some reason, the names on the schematic don't match the names inside the FPGA, which can make things confusing.

Ok, I now see that you want to use the SMA_RX and SMA_TX. That is GTX_X0Y18.
A lot of stuff around the GTX transceivers are hardwired in the FPGA, so the freedom to connect things is very restricted.
The MGT reference clock must come from an IBUFDS_GTXE1 primitive, and that primitive can only be connected to dedicated MGT refclk pins.
The MGT refclk for a GTX can only come from the dedicated pins for the bank, or from one of the adjacent banks.

It is not possible to get the MGT refclk from a MMCM.
The only realistic alternatives in this case are 125 MHz or the SMA REFCLK (200 MHz if taken from the board itself).

std_match said:

The MGT refclk for a GTX can only come from the dedicated pins for the bank, or from one of the adjacent banks.

It is not possible to get the MGT refclk from a MMCM.
The only realistic alternatives in this case are 125 MHz or the SMA REFCLK (200 MHz if taken from the board itself).

Click to expand...

You mean except for the 125 MHz clock, I have to connect an external clock to SMA_REFCLK even if I want to use 200MHz clock for GTX?
If yes, how can I get an output clock from the board?

mrmsh said:

You mean except for the 125 MHz clock, I have to connect an external clock to SMA_REFCLK even if I want to use 200MHz clock for GTX?
If yes, how can I get an output clock from the board?

Click to expand...

Yes, you must use 125 MHz or the SMA connectors as the MGT reference clock.
It seems that the board internal 200 MHz clock is not available on any SMA connectors. You can try to route it inside the FPGA to the "USER SMA GPIO" connectors. It should at least be easy to divide the 200 MHz clock by 2 to get 100 MHz on those connectors. Please check if you can use 100 Mhz instead of 200 MHz as the MGT reference clock. When you connect a differential clock via SMA connectors, both cables must have the same length.