FPGA project where clock for it is external signal - what rules for designing?

[FlyingDutch]

Hello,

let's assume that we are implementing comunication protocol where main clock is external signal (to FPGA circuit) for example 33 MHz . We likely have to input this external clock signal to "clock capable pin" of FPGA. But I don't fully understand how consequences it has to FPGA project. What if internal clock of FPGA board is much higher than taht external clock = for example 100 Mhz. How impact such situation has to FPGA project, are there any special rules which one have to follow. How impact it has to simulation process and timing constraints for such circuit.
Could somebody describe such rules for project of clock external to FPGA circuit?

Best Regards

 

[barry]

Why not use your external “main” clock as your, you know, MAIN CLOCK? Why bother with the ”internal clock”?

But if you ARE going to use both clocks then you need to be aware of clock domain crossings. There’s plenty of information about that on the internet. And, yes, there are plenty of rules about that. You need to educate yourself.

 

[FvM]

All clock sources on the FPGA board are external to the FPGA, e.g. crystal oscillators. In so far it's not clear to me what you are specifically asking.

Most recent FPGA have internal PLLs that can generate multiple clocks from one input source. Clock frequencies are selected according to design requirements.

 

[FlyingDutch]

Hello @FvM,

I just want to simplify project (first I made assumption that 33 MHz will be generated by PLL on FPGA). Now then I am sure that this clock signal will come from external circuit , I can remove IP Core with "Clocking Wizard" (PLL).

Thanks for coment and Regards

 

[dpaul]

But I don't fully understand how consequences it has to FPGA project.

Run Timing Analysis of your design, you'll have fun there!

1. You can feed the 33M to a MMCM/PLL and generate many other higher freq clocks and use them.
2. You can also feed this 33M off-chip clock to a BUFG and then use it anywhere in the design.

btw - This protocol you are using to bring in data at 33MHz, does it involve source synchronous clocking?

 

[dpaul]

What if internal clock of FPGA board is much higher than taht external clock = for example 100 Mhz.

I do not understand this. In a custom design, you are free to set the on-board oscillator to a desired frequency and bring that clock in to the FPGA. Then again, you can have clocks and data coming in to the FPGA from other on-board sources (e.g. another FPGA delivering clock and some data or a uC/uP with full custom interface with the FPGA)

 

[FlyingDutch]

I do not understand this. In a custom design, you are free to set the on-board oscillator to a desired frequency and bring that clock in to the FPGA. Then again, you can have clocks and data coming in to the FPGA from other on-board sources (e.g. another FPGA delivering clock and some data or a uC/uP with full custom interface with the FPGA)

Hello,

this is the situation when external (to FPGA) clock is coming from uC circuit.

Thanks for your answer and regards