arve9066
Member level 2
Code:
--UART RX
PROCESS(clk)
BEGIN
IF(clk'EVENT AND clk='1')THEN
--
if (RX_FLG = '0' AND RX_LINE='1') then
uart_ack <= '0';
end if;
--
IF(RX_FLG='0' AND RX_LINE='0')THEN
RX_INDEX<=0;
RX_PRSCL<=0;
RX_BUSY<='1';
TX_START <= '0';
RX_FLG<='1';
END IF;
IF(RX_FLG='1')THEN
RX_DATAFLL(RX_INDEX)<=RX_LINE;
IF(RX_PRSCL<868)THEN
RX_PRSCL<=RX_PRSCL+1;
ELSE
RX_PRSCL<=0;
END IF;
IF(RX_PRSCL=434)THEN
IF(RX_INDEX<9)THEN
RX_INDEX<=RX_INDEX+1;
ELSE
IF(RX_DATAFLL(0)='0'AND RX_DATAFLL(9)='1')THEN
DATA<=RX_DATAFLL(8 DOWNTO 1);
LOOPDATA(7 DOWNTO 0) <= DATA;
uart_data(7 DOWNTO 0) <= DATA;
uart_ack <= '1';
ELSE
DATA<=(OTHERS=>'0');
END IF;
RX_FLG<='0';
RX_BUSY<='0';
-- uart_ack <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;I am using a Spartan 6 FPGA with clock signal 100Mhz receiving serial data at 115200 baud. I need an acknowledge signal uart_ack that goes high only when the valid data is received and all other times till the 8 bits are completely received, it should remain 0. Do you think the above code will work? I am particularly interested in the location of the uart_ack signal in the code to satisfy my requirements. There are other data being sampled every 10 ns by the clock and this one byte of UART data should be only one sample in the stream of data which I am trying to ensure by checking the status of the uart_ack signal
