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OpAmp is supplied between +-15V and connecto to FPGA pin

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flote21

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Hello guys,

I have designed the sch attached. I am wondering if I could burn an FPGA pin in the power on/off of the board because this OpAmp is supplied to +-15. Could it be while the power on of the board the output of the OpAmp is at 15V and therefore it can burn the FPGA pin?

Thanks in advance.

opamp.jpg
 

Hi,

without special circuitry it is not predictable what happens during power up.
Especially here where you have at least three supplies: +15V, -15V, and the FPGA supply.

In any case I recommend to use some (FPGA) protecting circuit. I tshould limit the max voltage to the FPGA pin and/or limit the current into the FPGA pin.

If accidentally the OPAMP outputs some higher voltage than the rated FPGA supply current then the FPGA may become damaged.
This should be clearely documented in the "Absolute maximum ratings" in the FPGA datasheet.

Klaus
 

The problem is, as Klaus has explained, power supply sequencing and ramp up.

The larger problem is whether the +15 and -15 supplies ramp up towards regulation at the exact same rate. It can be done, but you would have to carefully trim the compensation loop, filter caps, load currents, etc.
Also, the +5 volt supply should be sequenced earlier than the +/-15 supplies.
National Semi had an old app note dealing with precisely this issue.

Now, if you cannot guarantee an equal ramp up and/or proper sequencing, the second best option is to use a 10k resistor in series with the op output ant then a BAT54S to protect the FPGAs input.
 

You mean doing something like the pic attached?

FPGA_ProtectionCircuit.jpg

schmitt trigger said:
The problem is, as Klaus has explained, power supply sequencing and ramp up.

The larger problem is whether the +15 and -15 supplies ramp up towards regulation at the exact same rate. It can be done, but you would have to carefully trim the compensation loop, filter caps, load currents, etc.
Also, the +5 volt supply should be sequenced earlier than the +/-15 supplies.
National Semi had an old app note dealing with precisely this issue.

Now, if you cannot guarantee an equal ramp up and/or proper sequencing, the second best option is to use a 10k resistor in series with the op output ant then a BAT54S to protect the FPGAs input.
Click to expand...
 

Hi,

You mean doing something like the pic attached?
Click to expand...
What should this be?
Weird pin names, no voltage limitation, no current limitation, no resistor at the opamp output, no BAT54S, still +/-15V...

I´m confused.

Klaus
 

To protect the FPGA input if it's not powered but the op amp is, I would use the 10k series resistors plus two Schottky protection diodes, one to V+ (anode to input) and one to ground (cathode to input).
 

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