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Designing Edge Detector Verilog Logic

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ammar_kurd

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What I want to do is to detect the raise of signal1 then at the fall of signal2 I want to do some logic but it must be in this order, something like this.

Code: 
always@(posedge signal1) begin

@(negedge signal2) begin
\\ do some logic
end

end

how to synthesize this with Verilog?

Thanks in advance.

 

you diagram does not match your description of what you want to do...which is the correct description?

Just looking at the code and using your text description...you can not use @(negedge signal2) within an always block it's illegal syntax.

If you need to detect the edge you have to either sample the signal (after synchronizing it to the clock) and perform a falling edge detection using a FF to delay the signal (after the synchrnoizer) and checking if the old state of the signal is 1 while the most recent state of the signal is 0.

the other option (not recommended) is to use a separate falling edge triggered FF that has it's D input set to 1 and feedback from some other logic to reset the FF back to 0 after having detected the edge and doing whatever need to be done. If you use this method you'll have lots of timing issues to contend with and lots of timing constraints that will be necessary to make the design work.
 

sorry about the confusion the diagram is the correct description, I switched between signal1 and signal2 in the description.

- - - Updated - - -

ads-ee said:
sample the signal (after synchronizing it to the clock) and perform a falling edge detection using a FF to delay the signal (after the synchrnoizer) and checking if the old state of the signal is 1 while the most recent state of the signal is 0.
Click to expand...

Can you please elaborate more regarding this option?
 

I’m not expert on this area, therefore the following code may contain syntactical and conceptual errors, but I think you could start trying something like that. It’s not yet synchronized as ads-ee mentioned, but you could check if it perform the behavior depicted at the above waveform.
Code: 
always @ ( posedge signal1 or negedge signal2 )
begin
      if  ( signal1 = 1 ) and ( signal2 = 0 )
            begin
                 \\ do some logic
            end
end
 

Andre's suggestion is an incorrect description of an asynchronous always block (you can't distinguish between the edges in a combinational always block. If you use that code you would be attempting to describe the follwong combinational logic.
Code: 
alway @* begin
  if (signal1 && !signal2) begin 
    // do this stuff
  end
end
Which doesn't seem like what you've described. Besides swapping the signal1 and signal2 description yeilds (along with paraphrasing a little....):
After the rising edge of signal2 detect the falling edge of signal1 and then do something after this event occurs.

But in reality I'm not sure this is what you need as you probably came up with this because you don't know how to handle whatever problem you were having originally...(basically I suspect this is an XY problem).

Signal1 looks like a clock, is it? and the signal2 looks like some event that occurs that you are trying to detect. If the signal2 is generated based on the signal1 (clk) then you don't have to synchronize it. If what you are trying to detect is the rising edge of signal2 then this is how you do it:
Code Verilog - [expand]
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// assuming that signal1 is a clock and signal2 is synchronous to signal1 (from some other logic clocked by signal1)
  wire signal1;
  wire signal2;
  reg signal2_dly;
  reg redge;
  always @(posedge signal1) begin
    signal2_dly <= signal2;
    redge <= ~signal2_dly & signal2;
  end


If you need to synchronize it then the following would be needed.
Code Verilog - [expand]
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// assuming that signal1 is a clock and signal2 is asynchronous to signal1
  wire signal1;
  wire signal2;
  reg [2:0] sig2_sync;
  reg redge;
  always @(posedge signal1) begin
    sig2_sync <= {sig2_sync[1:0], signal2};
    redge <= ~sig2_sync[2] & sig2_sync[1]; // [0] & [1] are part of the two stage syncrhonizer
  end
 
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