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[SOLVED] Is there any other method instead using class in systemverilog?

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u24c02

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Hi.

As I know the class is used to combine properties and methods like task and function etc... .

But, here is my question that what if there are 3 tasks, then I want to make 2 classes.
For exampl, c1 of class be consisted with a,b tasks and c2 of class be consisted with b,c tasks.
So is this proper methodology by using class?
And what is the benefit by using class instead of using directly use task and function?
 

"class" lacks synthesis support in most/all tools. For simulation it is fine.

In this case, you want to have a base class and two derived classes. the base class will define b, and the derived classes will define a or c.

classes are a convenience. In languages without classes (VHDL/Verilog/C), developers invent class-like constructs. They might not realize it at first.
 

Classes are very useful when encapsulating data structures and separating cycle based simulation from transaction level modelling.
For example - you can design a class that encapsulates a data packet, and they build up a stream of data packets away from the cycle based interface - this makes data generation and prediction much easier.
 

u24c02 said:
But, here is my question that what if there are 3 tasks, then I want to make 2 classes.
For exampl, c1 of class be consisted with a,b tasks and c2 of class be consisted with b,c tasks.
So is this proper methodology by using class?
And what is the benefit by using class instead of using directly use task and function?
Click to expand...

class C1 - contains task a, task b
class C2 - contains task b, task c

Best way to achieve this in any Object Oriented Programming such as SV.

define class C1 with task a and b.
extend class c2 from class c1 and define with task c in it.


Benefit: you don't have to redefine task b in class c2 as c2 will have access to all task/variables of c1. Please refer to concepts of OOP in SV or any language to understand more.
 

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