xiaoanime
Newbie level 2
This is the vhdl code I had, I am not sure how write a test bench for it. Anyone able to guide me through this?
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity ltp_controller is port ( iCLK: in std_logic; -- LCD display clock iRST_n: in std_logic := '0'; -- system reset -- SDRAM Side iREAD_DATA1: in std_logic_vector (15 downto 0); -- R and G iREAD_DATA2: in std_logic_vector (15 downto 0); -- B oREAD_SDRAM_EN: out std_logic; -- read sdram data control signal -- LCD SIDE oHD: out std_logic; -- LCD Horizontal sync oVD: out std_logic; -- LCD Vertical sync oDEN: out std_logic; -- LCD DataEnable oLCD_R: out std_logic_vector (7 downto 0); -- Red out oLCD_G: out std_logic_vector (7 downto 0); -- Green out oLCD_B: out std_logic_vector (7 downto 0) -- Blue out ); end ltp_controller; architecture behave of ltp_controller is constant H_LINE: natural := 1056; constant V_LINE: natural := 525; constant Hsync_Blank: natural := 46; -- H_SYNC + H_Back_Porch constant Hsync_Front_Porch: natural := 210; constant Vertical_Back_Porch: natural := 23; -- V_SYNC + V_BACK_PORCH constant Vertical_Front_Porch: natural := 22; -- ieee.numeric_std.all start signal x_cnt: unsigned (10 downto 0); signal y_cnt: unsigned (9 downto 0); signal read_red: std_logic_vector (7 downto 0); signal read_green: std_logic_vector (7 downto 0); signal read_blue: std_logic_vector (7 downto 0); signal display_area: std_logic; signal mhd: std_logic; signal mvd: std_logic; signal mden: std_logic; begin oread_sdram_en <= '0' when x_cnt > Hsync_Blank - 2 and -- 214 x_cnt < H_LINE - Hsync_Front_Porch - 1 and -- 1015 y_cnt > Vertical_Back_Porch - 1 and -- 34 y_cnt < V_LINE - Vertical_Front_Porch else -- 515 '1'; display_area <= '1' when x_cnt > Hsync_Blank - 1 and -- > 215 x_cnt < H_LINE - Hsync_Front_Porch and -- < 1016 y_cnt > Vertical_Back_Porch - 1 and y_cnt < V_Line - Vertical_Front_Porch - 1 else '0'; read_red <= iREAD_DATA2(9 downto 2) when display_area = '1' else (others => '0'); read_green <= iREAD_DATA1(14 downto 10) & iREAD_DATA1(14 downto 12) when display_area = '1' else (others => '0'); read_blue <= iREAD_DATA2(9 downto 2) when display_area = '1' else (others => '0'); X_COUNTER:process (iRST_n, iCLK) begin if iRST_n = '0' then x_cnt <= (others => '0'); elsif rising_edge(iclk) then if x_cnt = H_LINE - 1 then x_cnt <= (others => '0'); mhd <= '0'; else x_cnt <= x_cnt + 1; mhd <= '1'; end if; end if; end process; Y_COUNTER:process (iRST_n, iCLK) begin if iRST_n = '0' then y_cnt <= (others => '0'); elsif rising_edge(iclk) then if x_cnt = H_LINE - 1 then if y_cnt = V_LINE - 1 then y_cnt <= (others => '0'); else y_cnt <= x_cnt + 1; end if; end if; end if; end process; LCD_VSYNC:process (iCLK, iRST_n) begin if iRST_n = '0' then mvd <= '1'; elsif rising_edge(iCLK) then if y_cnt = 0 then mvd <= '0'; else mvd <= '1'; end if; end if; end process; LCD_ENAB:process (iCLK, iRST_n) begin if iRST_n = '0' then mden <= '1'; elsif rising_edge(iCLK) then if display_area = '1' then mden <= '1'; else mden <= '0'; end if; end if; end process; BLANK_RESET: process (iCLK, iRST_n) begin if iRST_n = '0' then oHD <= '0'; oVD <= '0'; oDEN <= '0'; oLCD_R <= (others => '0'); oLCD_G <= (others => '0'); oLCD_B <= (others => '0'); elsif rising_edge(iCLK) then oHD <= mhd; oVD <= mvd; oDEN <= mden; oLCD_R <= read_red; oLCD_G <= read_green; oLCD_B <= read_blue; end if; end process; end architecture;
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