frequency counter/meter in VHDL

omerysmi said:

I have tried to count rising edges of the main clock and according to this to calculate the measured frequency but it's not really good.

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std_match said:

The simplest approach is to use the fixed main clock to create a fixed measuring time. Since the DE1 board only has 4 digits you only need 10 kHz resolution.
If you count the unknown input signal cycles (= rising or falling edges) during 100 us you will directly get the frequency with 10 kHz resolution.

You can count the unknown signal in two ways:

1. Use it as a clock input to drive a counter. Since the 7-segment display on the DE1 isn't multiplexed, you can drive it directly from the input clock domain, but there are drawbacks. A more "serious" design is to drive the display from the base clock domain. This requires clock domain crossing logic to transfer the counted value to the base clock domain.

2. Synchronize the input signal to the base clock domain and do the counting with a state machine counter. This requires the base clock to be at least twicr the measured frequency. You can use a PLL to increase the base clock to 100 MHz or more.

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omerysmi said:

There is a way to make a simulation for 1Hz clock? because the vwf simulation time base is til 100us

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std_match said:

You can have any timebase in the simulation and in the waveform, but it is not smart to mix very different frequencies (like 1Hz and 50 MHz) in the same simulation. That will be a waste of simulation time. There should be no fixed "time base" for the simulation, you can use what you want.

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TrickyDicky said:

In modelsim just type

run 1 s

THat will run the simulation for 1 s

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std_match said:

Regardless of the simulator, it is not a good idea to simulate 1 second if there is a 50 MHz clock in the design. You probably don't need more than 50 us simulation to fully test the frequency counter.

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fcounter is
port(clk, m_clk, reset : in std_logic;
	  fout	            : out integer range 0 to 50E6);
end entity;

architecture arc of fcounter is
signal pulses : integer range 0 to 50e6:=0;
signal counter : integer range 0 to 50e6:=0;
signal flag : std_logic;
begin

	process(clk,reset)
		begin
		if reset='0' then
			pulses<=0;
		elsif rising_edge(clk) then
			if counter<50e6 then
				if m_clk='1' and flag='1' then
					pulses<=pulses+1;
					flag<='0';
				elsif m_clk='0' then
					flag<='1';
				end if;
				counter<=counter+1;
			else
					counter<=0;
					fout<=pulses;
					pulses<=0;
			end if;
		end if;
	end process;
end arc;

std_match said:

How long time does it take to simulate 100 us?
Multiply that by 10000 to get the simulation time for 1 second.

You should use as lower value for simulation and debugging, and then use the real value when implementing it in a real FPGA. You can use generics to automatically use a different value for simulation.

In your case there is no meaning to measure for 1 second since your frequency counter only has 4 digits. Count for 100 us. The count value can then directly be used on the display as MHz with two decimal places.

The frequency resolution is 1/(measuring time).

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std_match said:

Change the 50e6 constants to a smaller value to reduce the simulation time.

If you change to Modelsim you can simulate as long as you wish, but it is a waste of time to simulate a 50 MHz clock for 1 second when almost nothing happens.

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std_match said:

Change the 50e6 constants to a smaller value to reduce the simulation time.

If you change to Modelsim you can simulate as long as you wish, but it is a waste of time to simulate a 50 MHz clock for 1 second when almost nothing happens.

Click to expand...