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Power pads in TSMC library

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mvvijay78

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io pad lvs

Hi,
I would like to know how to use the PVDD1SDG and PVDD2SDG power pads in the TSMC pad library.It is given that the VDD1 pad is to be used for Core voltage and the VDD2 pad is to be used for IO voltage.But each of these pads have VDD: ,VSS: ,VSSPST: ,VD33 pins.How to connect the 1.8V applied to the pad input to the internal declared global net used to create the core rings.
Basically can anypne explain how do these power pads work?
Regards
Vicky
 

tsmc library

A brief explanation:

Basically you should use power routing functionality of the layout tool to connect power pad to internal power mesh. You dont have to do it yourself.The task depends on the tool you use.

Here is an example for SOC Encounter to do power routing:
1)edit the IO pad configuration file to addin the power pads. Then reload it into SOC Encounter. Thus the power pad is put into the layout.
2)Define the global power net
3)Define and generate power strap & rings for core area
4)Call PowerRout to do power routing.This includes connecting power rails for std-cell, connecting pad rings, and connecting power pad to internal power mesh.
5)If the tool generate some DRC errors, correct it automatically or manually.
 

tsmc pad

Hi,

As I remembered:

PVDD1SDG - VDD pad for Core and connected to VDD(or GND) in LVS netlist
PVSS1SDG - VSS pad for Core and connected to VSS in LVS netlist

PVDD2SDG - VDD pad for IO and connected to VDDPST in LVS netlist
PVSS2SDG - VSS pad for IO and connected to VSSPST in LVS netlist

Hope this can help!!
 

tsmc pad library

Hi,
I am using magma blast fusion.Any idea how to do it in this tool.
Regards
Vicky
 

pads 2005 lib

Even i am using MAGMA and facing a similar problem

Any expert please help

thanks in advance
 

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