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XILINX bus problem in schematic

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Jiadong Yao

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QQ截图20150221205323.png

i am working with xilinx. I got the assignment to make a 16 bit binary counter and a loadable up&down counter. Now i have made it. And i have tested them. They all work well.

The last step is to combine two counters with multiplexer.
This is the requirement.QQ截图20150221205632.png

I have tries many ways to implement. but i always got error.

Because the MUX can only allow one data to go through (the width is 1), the output of the bus cannot go through the MUX. I dont know how to do so.

Another problem is that how can i get part of the signal i.e. the upper 8 bits of the CNT16BIT(15:0)???

Thank you
Jiadong

- - - Updated - - -

QQ截图20150221212731.png
I make a test file. When i try to make connection like this, i got the error
QQ截图20150221212825.png

I dont know how to make the connection.

- - - Updated - - -

if you do like this,QQ截图20150221213904.png
you got the errorQQ截图20150221213952.png
 

For your 2nd question the output is always 8 bits(from one of the 2 counters). This means that the lower 8 bits of the 16 bit counter are not used.
For driving 8 bits of the output, you will need 8 2:1 muxes. Each mux will take one input from the 8 bit counter and the other from the 16 bit counter. I assume that the select line to this mux comes from the external world.
 

For your 2nd question the output is always 8 bits(from one of the 2 counters). This means that the lower 8 bits of the 16 bit counter are not used.
For driving 8 bits of the output, you will need 8 2:1 muxes. Each mux will take one input from the 8 bit counter and the other from the 16 bit counter. I assume that the select line to this mux comes from the external world.

Thank you very much!!!!!
Why am i always being so stupid......
I was thinking of using one mux...... Why not use 8!!!
Problem solved!!!
 

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