There are all different languages not really concerned with each other !!!! Verilog and Vhdl are HDL (Hardware description language) and languages such as 'e' and 'vera' are HVL (Hardware verification languages) ..'e' is used for verification and not for designing hardware .. now why e and not just verilog or vhdl to do verification also ? .. 'e' is a content oriented language which allows you to do verification at a much higher abstraction .. please look at the introduction section that is there is specman home page ... you will get a very good answer ..abhineet22 said: