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Maybe because this is oxide rupture, not silicon "breakdown"
(which has better-understood impact ionization / avalanche
mechanisms in a material whose composition is pretty well
known - gate oxide, there are many nuances as far as the
defectivity, growth-mechanics-driven density / uniformity
of bonds & vacancies, even gross composition).
Can you tell me which type of result/plot between drain current and drain voltgate at gate voltage 0v, -10v and further increase in negative voltage we get in LDMOS device ?
At Vgs=0V we don't get the zero current so why we could not success whats the reason for this .
And in run time process we found a warning that one contact bot sides of junction whats its means and whats problem plz help me to find out the proper result .
In LDMOS , we use only uniform doping or gaussian distribution in atlas silvaco simulator and at channel also I use only uniform doping .
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