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In VHDL,can we use a "real" in entity port list..

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nick123

nick123

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Code VHDL - [expand]
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entity MY_PROG is 
port( 
Real : in std_logic_vector (31 downto 0); 
Imag : in std_logic_vector (31 downto 0); 
Realo : out std_logic_vector (31 downto 0); 
Imago : out std_logic_vector (31 downto 0); 
clk, Request: in std_logic; 
); 
end MY_PROG ;


Is this valid to use "real" as a input port list in the entity as its predefined in vhdl.
 
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No. You said it yourself. "real" is a reserved word in VHDL.
 

VHDL reserved words are listed in the LRM. "real" isn't a reserved word. As long as you don't use the predefined real type in your design entity, you can probably use the name for other other objects, e.g. a port name. But why should you? It causes confusion, starting with the syntax highlighter.

Somehow a useless discussion.
 
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    nick123

    nick123

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shaiko said:
No. You said it yourself. "real" is a reserved word in VHDL.
Click to expand...

thank you for your reply sir but FvM in the next comment said we can use it.., i think he's right.

-------------------

Thank you so much Sir for you reply..just out of curiosity i asked this "useless" question, but i get to know and learn something i didn't knew before and that's how it became useful for me..thank you again.
FvM said:
VHDL reserved words are listed in the LRM. "real" isn't a reserved word. As long as you don't use the predefined real type in your design entity, you can probably use the name for other other objects, e.g. a port name. But why should you? It causes confusion, starting with the syntax highlighter.

Somehow a useless discussion.
Click to expand...
 
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