rakeshk.r
Member level 2
HI, I have a component 'test1' which consist of only 2 instances of demux. The default width of demux port is set to 32 using 'Generic' statement (you can have a look at the code below).
Now I override this default value "32" to 16 for one the instances(U_0) using their object properties as shown in pic1 below.
Now the test1 struct has a generic table where i need to specify width's default value and I have done it as shown in pic2 below.
Now I compile and simulate the test1 component, So the code for interconnections in 'test1' component is generated by HDL designer tool itself and i have pasted it below (just for reference).
Now I get error in modelsim: ** Fatal: (vsim-3348) Port size (16) does not match actual size (32) for port '/test1/U_0/datain'.
Time: 0 ns Iteration: 0 Instance: /test1/U_0 File: /edu/../project_pf_lib/hdl/demux_logic.vhd Line: 17
I don't know why the value 16 is not taken into account and where am I going wrong ? I want to know how generics are handled for the instances of a component in HDL designer tool. I don't think it is more of a logic problem. I feel one who has good experience in Mentor Graphics HDL designer might help me better. Thank you.
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY demux IS
GENERIC( width : positive := 32 );
PORT(
datain : IN signed (width-1 DOWNTO 0);
sel : IN std_logic;
out0 : OUT signed (width-1 DOWNTO 0);
out1 : OUT signed (width-1 DOWNTO 0)
);
-- Declarations
END demux ;
--
ARCHITECTURE logic OF demux IS
BEGIN
demuxlogic:process(datain,sel)
begin
case sel is
when '0' => out0 <= datain; out1 <= (others=>'0');
when '1' => out1 <= datain; out0 <= (others=>'0');
when others => out0 <= (others=>'0'); out1 <= (others=>'0');
end case;
End process;
END ARCHITECTURE logic;Now the test1 struct has a generic table where i need to specify width's default value and I have done it as shown in pic2 below.
Now I compile and simulate the test1 component, So the code for interconnections in 'test1' component is generated by HDL designer tool itself and i have pasted it below (just for reference).
Code:
-- Generated by Mentor Graphics' HDL Designer(TM) 2010.2a (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY test1 IS
GENERIC(
width : positive := 32
);
PORT(
datain : IN signed (width-1 DOWNTO 0);
datain1 : IN signed (width-1 DOWNTO 0);
sel : IN std_logic;
out0 : OUT signed (width-1 DOWNTO 0);
out1 : OUT signed (width-1 DOWNTO 0);
out2 : OUT signed (width-1 DOWNTO 0);
out3 : OUT signed (width-1 DOWNTO 0)
);
-- Declarations
END test1 ;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY project_pf_lib;
ARCHITECTURE struct OF test1 IS
-- Architecture declarations
-- Internal signal declarations
-- Component Declarations
COMPONENT demux
GENERIC (
width : positive := 32
);
PORT (
datain : IN signed (width-1 DOWNTO 0);
sel : IN std_logic ;
out0 : OUT signed (width-1 DOWNTO 0);
out1 : OUT signed (width-1 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : demux USE ENTITY project_pf_lib.demux;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
U_0 : demux
GENERIC MAP (
width => 16
)
PORT MAP (
datain => datain,
sel => sel,
out0 => out0,
out1 => out1
);
U_2 : demux
GENERIC MAP (
width => 32
)
PORT MAP (
datain => datain1,
sel => sel,
out0 => out2,
out1 => out3
);
END struct;Time: 0 ns Iteration: 0 Instance: /test1/U_0 File: /edu/../project_pf_lib/hdl/demux_logic.vhd Line: 17
I don't know why the value 16 is not taken into account and where am I going wrong ? I want to know how generics are handled for the instances of a component in HDL designer tool. I don't think it is more of a logic problem. I feel one who has good experience in Mentor Graphics HDL designer might help me better. Thank you.
