library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity true_dual_port_ram is
port (clk : in std_logic;
we : in std_logic;
en : in std_logic;
addr1 : in std_logic_vector(5 downto 0);
di1 : in std_logic_vector(15 downto 0);
do1 : out std_logic_vector(15 downto 0));
we2 : in std_logic;
en2 : in std_logic;
addr2 : in std_logic_vector(5 downto 0);
di2 : in std_logic_vector(15 downto 0);
do2 : out std_logic_vector(15 downto 0));
end true_dual_port_ram;
architecture ram_arch of true_dual_port_ram is
type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0);
signal RAM : ram_type;
begin
process (clk)
begin
if clk'event and clk = '1' then
if en = '1' then
if we = '1' then
RAM(conv_integer(addr)) <= di;
else
do <= RAM( conv_integer(addr));
end if;
end if;
end if;
end process;
process (clk)
begin
if clk'event and clk = '1' then
if en2 = '1' then
if we2 = '1' then
RAM(conv_integer(addr)) <= di2;
else
do2 <= RAM( conv_integer(addr));
end if;
end if;
end if;
end process;
end ram_arch;signal count : unsigned(n downto 0);
process(clk, reset)
begin
if reset = '1' then
count <= (others => '0');
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process;
Something like that.
entity bram is
port(clk:in std_logic;
en1,en2:in std_logic;
we1,we2:in std_logic_vector(o downto o);
data:in std_logic_vector(31 downto 0);
addr:in std_logic_vector(15 downto 0);
dataouta,dataoutb:out std_logic_vector(31 downto 0));
end bram;
architecture behavioral of bram is
COMPONENT DPM
PORT(clka:in std_logic;
ena:in std_logic;
wea:in std_logic_vector(0 downto 0);
addra:in std_logic_vector(15 downto 0);
dina:in std_logic_vector(31 downto 0);
douta:out std_logic_vecor(31 downto 0);
clkb:in std_logic;
enb:in std_logic;
web:in std_logic_vector(0 downto 0);
addrb:in std_logic_vector(15 downto 0);
dinb:in std_logic_vector(31 downto 0);
doutb:out std_logic_vector(31 downto 0));
END COMPONENT;
type state is (initial,input,writestate,readstate);
signal currentstate,nextstate:state;
signal addra,addrb:std_logic_vector(15 downto 0);
signal dina,dinb:std_logic_vector(31 downto 0);
signal wea,web:std_logic_vector(0 downto 0);
signal douta,doutb:std_logic_vector(31 downto o);
begin
our_instance_name:DPM
PORT MAP(
clka=>clk,
ena=>en1,
wea=>wea,
addra=>addra,
dina=>dina,
douta=>douta,
clkb=>clk,
enb=>en2,
web=>web,
addrb=>addrb,
dinb=>dinb,
doutb=>doutb);
process(clk,nextstate)
begin
if (clk'event and clk='1') then
case currentstate is
when initial=>
addra<="zzzzzzzzzzzzzzzz";
dina<="zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz";
addrb<="zzzzzzzzzzzzzzzz";
dinb<="00000000000000000000000000000000";
dataouta<="00000000000000000000000000000000";
dataoutb<="00000000000000000000000000000000";
if (en1='1')then
currentstate<=input;
else
currentstate<=initial;
end if;
when input=>
wea<="1";
addra<=addr;
dina<=data;
if (we1=''1'') then
currentstate<=writestate;
else
currentstate<=initial;
end if;
when wriestate=>
if (addra="1111111111111111") then
currentstate<=initial;
else
wea<="0";
dataouta<=douta;
dataoutb<=doutb;
end if;
if (en2='1') then
if(we2="0") then
currentstate<=readstate;
web<="0";
addrb<=addra;
else
currentstate<=initial;
end if;
end if;
when readstate=>
currentstate<=writestate;
end case;
end if;
end process;
dataouta<=douta;
dataoutb<=doutb;
process(clk)
begin
if(clk='1') then
nextstate<=currentstate;
end if;
end process;
end behavioural;It has errors. You need a VHDL simulator to check and correct it.
And hopefully proceed from vague descriptions like "ram write/read code with address counters" to an explicite design specification.
entity wriread is
Port ( clk : in STD_LOGIC;
en1,en2 : in STD_LOGIC;
we1,we2 : in STD_LOGIC_VECTOR (0 downto 0);
data1,data2 : in STD_LOGIC_VECTOR (31 downto 0);
addr1,addr2 : in STD_LOGIC_VECTOR (15 downto 0);
datao1,datao2 : out STD_LOGIC_VECTOR (31 downto 0));
end wriread;
architecture Behavioral of wriread is
type mem_type is array (0 downto 65535) of std_logic_vector(31 downto 0);
type state is (initial,input,write_initiate,write_complete);
signal mem:mem_type;
signal count: integer range 0 to 65535;
signal currentstate,nextstate:state;
begin
process(clk,currentstate)
begin
if(clk'event and clk='1') then
currentstate<=initial;
case currentstate is
when initial =>
datao1<="00000000000000000000000000000000";
datao2<="00000000000000000000000000000000";
if (en1='1') then
currentstate<=input;
else
currentstate<=initial;
end if;
when input =>
if(we1="1") then
currentstate<=write_initiate;
else
currentstate<=initial;
end if;
when write_initiate =>
for count in 0 to 65535 loop
mem(conv_integer(addr1))<=data1;
end loop;
currentstate<=write_complete;
when write_complete=>
for count in 0 to 65535 loop
datao1<=mem(conv_integer(addr1));
end loop;
end case;
end if;
end process;
end Behavioral;
ortability/export/Port_Main.h:127:1.16 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com