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[SOLVED] Conflict between blocking statement and forever statements

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rahul.achates

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Hi

We all know blocking statement block the execution of next statement until current statement execution and assignment completed. but when we use forever in verilog , should be use non-blocking type of statement ? otherwise all statement will not executes in parallel .. .

Rahul
 

A non-blocking assignment statement is a slight misnomer. The statement still blocks until it is finished executing, then the next statement executes. It's just the the update to the LHS is scheduled for a later time.

Just like the always construct, the attached statement or block of statements of a forever loop better have at least one statement that actually blocks execution. Otherwise the simulation will hang in that loop.
 

hi dave_59

That is not answered of my question ... should be use blocking statement or non-blocking statement in forever loop ?
 
You need to provide more context for your question to give you a meaningful answer. Both of these pieces of code are perfectly acceptable.


Code: 
initial begin
          clk = 0;
          #10
          forever
             #100  // blocking event control
             clk = ! clk;
  end


initial forever 
               @(posedge clk) // blocking event control
               q_shifted <= q;
First loop using blocking assignment statements, second loop uses non-blocking assignment statements. Both loops have a blocking event control statement that keep the simulation from hanging. Try writing a loop without it and you will see what I mean.
 

forever statement mean all statement will executes in parallel regardless of blocking or non-blocking , this is what forever loop says.

My question was .. should be use blocking or non-blocking in forever , and if blocking then why simulator executes all statement in parallel instead of executing statement like in normal blocking block.
 
rahul.achates said:
forever statement mean all statement will executes in parallel regardless of blocking or non-blocking , this is what forever loop says.
Click to expand...
That isn't what is written in 1800-2012 IEEE Standard for SystemVerilog LRM. ()

Dave_59 has already answered your question and if you don't believe his answer then read section 12.7.6 of the standard yourself.

Regards
 

ads-ee said:
That isn't what is written in 1800-2012 IEEE Standard for SystemVerilog LRM. ()

Dave_59 has already answered your question and if you don't believe his answer then read section 12.7.6 of the standard yourself.

Regards
Click to expand...

Go through my question .. this is not I have asked.

I know you need to put some timing delay otherwise simulator will hang .. but how does this related to my post ??

In other words, I have asked
should I use
forever begin
#5 clk <= !clk ;
#4 sig_a <= sig_b;
end

or should I use

forever begin
#5 clk = ~clk;
#4 sig_a = sig_b;
end


Thanks ..
 
They behave the same due to the blocking events #5 and #4. Why don't you try running a simulation with both forever loops, just make all the signals clocks with different names.
 

Your choice to use blocking or non-blocking assignment statements has nothing do do with the fact that they are inside a forever loop, or a for loop, or a case statement. The only thing that matters is there another process trying to read the signals you are assigning synchronized to the same event that you are writing the same set of signals. In your last post #8, you are only showing one process, and they are writing to clk and sig_a.
 

Thanks for the info dave ..

but the problem will start when there is dependency between signals. then blocking , non-blocking may create difference in output.


Anyhow, I have got my answer , in Verilog LRM , I found in forever loop , there is no concept on blocking. Even if you use blocking statement but because of forever loop, this will override and all statement will executes at same time.

Thanks for the effort.

Rahul
 
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