Solution for a VHDL code, what will synthesis produce?

I have a question???

Hi,

Would you please help me resolve the following question.I will appreciate you.
Thank you.

For the following VHDL, what will synthesis produce? Draw the resulting gate-level representation or logic equation representation.

library ieee;
use ieee. std_logic_1164.all;

entity function_ex is
port ( a1, a2, b1, b2 : in std_ logic;
en : in std_logic;
y1 : out std_ logic);
end entity;

architecture rtl of function_ex is

function xor_ fn (f1, f2 : std_ logic) return std_ logic is
variable r : std_ logic;
begin
r := f1 xor f2;
return r;
end function xor_fn ;

begin

xnor_ proc: process (b1, b2) is
begin
if (en = ‘1’) then
y1 <= xor_fn( a1,a2)
else
y1 <= xor_fn( b1,b2)
end if;

end process;
end architecture rtl;

Re: I have a question???

I have synthesized ut vhdl code in leonardo spectrum.. and ihave got the follin results... am uploadin the synthesized outputs..


*******************************************************

Cell: function_ex View: rtl Library: work

*******************************************************


Cell Library References Total Area

IBUF xis2e 5 x 1 5 IBUF
LUT4 xis2e 2 x 1 2 Function Generators
MUXF5 xis2e 1 x 1 1 MUXF5
OBUF xis2e 1 x 1 1 OBUF

Number of ports : 6
Number of nets : 14
Number of instances : 9
Number of references to this view : 0

Total accumulated area :
Number of Function Generators : 2
Number of IBUF : 5
Number of MUXF5 : 1
Number of OBUF : 1
Number of gates : 2
Number of accumulated instances : 9
***********************************************
Device Utilization for 2s50eft256
***********************************************
Resource Used Avail Utilization
-----------------------------------------------
IOs 6 178 3.37%
Function Generators 2 1536 0.13%
CLB Slices 1 768 0.13%
Dffs or Latches 0 2070 0.00%

-----------------------------------------------


Hope this helps.

with regards,

Re: I have a question???

Hi,

I cannot understand your answer.Is it syntheis produce?
How can I draw the gate-level representation or logic equation
representation?Thank you.

Added after 2 minutes:

Hi,

I got your picture for gate-level representation.Thank you