Fractional-N
Full Member level 1
Hi,
I have a VHDL code, and there is a FIFO ip core in the code. I have copied the .vhd files and .ucf files and also a .v file and ipcore_dir directory to another directory and I tried to synthesize the code but ISE gives the Error "Could not find module/primitive "
the code is a mixed VHDL and Verilog one.
what should I do? any help?
I have a VHDL code, and there is a FIFO ip core in the code. I have copied the .vhd files and .ucf files and also a .v file and ipcore_dir directory to another directory and I tried to synthesize the code but ISE gives the Error "Could not find module/primitive "
the code is a mixed VHDL and Verilog one.
what should I do? any help?