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Bandgap startup circuit simulation

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ccw27

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I have a bandgap with 2 startup circuits. When I run a transient analysis it takes very long to simulate. This has to do with the output waveform shown below. Is the circuit unstable? Or does it has to do with the 2 startup circuits?

By the way I am ramping the Vdd signal and plotting Vbg.

Thanks
 

I think it is unstable. Did you run AC analysis?
And what do you mean 2 startup circuits?
 

This is just a guess but from the waveform i see it could be a problem of the integration algoritm, try to select a diferent one.
 

How do I simulate the loop gain of this bandgap? Where do I break the loop? According to the paper the critical stability point is OP1 and M4. Basically I have 2 start-up circuit, one for constant gm and the other as shown below, but I don't think the problem is in the start up circuit.

Thanks
 

Usually I break the loop in two places and compare results. If they coincide it is OK.
You can break the loop at the input of OP1, but for calculation use differential signals. Or you can break the loop at the output of OP1 and gate of M4.
 

According to the paper, to guarantee the stability of this loop
Fu(LG)<Fu(op1)

From my simulation, it seems to be fine. But somehow the problem lies in the op1 and M4 loop because when I disconnect the loop and run a transient the simulation goes fast. So I am not sure what to do now? Anyone has any ideas?

Thanks

Added after 1 hours 15 minutes:

I think the problem of trying to ramp the supply voltage from 0 to Vdd is that op1 stops to track under 1.4 V (M4 is off). So when I do a transient analysis it takes very looong to simulate. But will this cause the output to never settle and ring forever ?? Any ideas anyone?

Thanks
 

You can break the loop by inserting into the feedback path two voltage controlled voltage sources with a very low frequency RC filter in between. Then insert a AC voltage source at the output. So you can analyse the openloop AC transfer without disturbing the DC oerating point. For a differential amplifier you have to take the volatge difference at the input.

Added after 1 minutes:

Could you plot also the internal of the opamps.
 

So basically when I ramp from 0.9 to 1.8 V the bandgap works fine, but when I go from 0 to 1.8 V it starts to oscillate. Does that mean that my bandgap is oscillating below 0.9 V supply? I checked the loop gain at 0.8V and the gain is negative and phase starts at -180. This has to do with PMOS M4 which is turned off.

Thanks
 

The possible oscillation is not in the basic PTAT loop but in the take over circuit for the initial startup. Isolate the startup by using an constant current source as startup instead.
 

makesure OP1 and OP2 are stable (>60 phase margin)
also, the combination of OP1 and M4 added another stage to your OP1, makesure the combination of OP1 and M4 is stable.
 

I think I found where the problem is. The loop gain in OP2 is unstable though I don't see where the loop is and how I can go about improving its phase margin. Anyone any ideas?

Thanks

Added after 4 hours 48 minutes:

Yea definetely loop gain of OP2 is unstable. I simulated using an ideal opamp and ran transient and everything goes fine. Any ideas how I can improve the phase margin of OP2 and M5 loop gain?

Thanks
 

Probably you can stabilize it the usual way. Just add a simple Miller capacitor in the last stage of OPA2, i.e. a capacitor connected between the input (gate) and the output (drain, OPA2 output) of your last gain stage inside OPA2
 

How can I generate PTAT from the bandgap above? It seems like it depends on TC of the resistor divider in the output.

Thanks
 

Will the transient simulation show the real chip behavior of bandgap including start-up circuit? I mean if the model was correctly characterized.
What will be other factor to let bangdap fail when wafer is out if WAT data is OK?
 

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