tommydidi
Member level 1
Guys,
I am design a NMOS LDO. Now I have finished the charge pump (switched cap) and working on the err amp. The questions I have for you guys are:
1. Do I need a buffer stage for the err amp?
2. How can I simulate the whole loop stability? Not sure how to model the charge pump, any idea?
Thanks.
I am design a NMOS LDO. Now I have finished the charge pump (switched cap) and working on the err amp. The questions I have for you guys are:
1. Do I need a buffer stage for the err amp?
2. How can I simulate the whole loop stability? Not sure how to model the charge pump, any idea?
Thanks.