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Database for synthesis and pattern generation

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vikas.m0502

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Hi,

Can anyone suggest, from where I can get the database for synthesis and pattern generation through rtl compiler ?
I need everything, verilog code(or netlist) library modules everything whatever is needed.

Thanks in advance.

Regards,
vik
 

well,
to do a synthesis, you need the RTL code and the liberty file which define the std cells/pad/memories/custom macros, to generate a netlist in verilog usually.
to insert the DFT (as scan chain), some synthesis tool could do it or used a dedicated tool, normaly the liberty with RTL or netlist is enough.
to do the pattern generation, the netlist and the std cells/pad/memories/custom macro model faults is needed to generate the scan patterns (for stuck-iddq-bridge-transition-small delay-UDFM).
 

Hi,
Thanks for ur reply.
But the the thing is I know about dft, all I wanted to know site or link to get all these things to get started.
 

If you have a tool, thn you need to find the docs in the tool directory itself..where you have the all information for start up.
 

I just have the tool.
I am asking for some database, means netlist,library modules etc.
From where can I get that ?
 

Netlist is not in the Database, Netlist is the design on which you are doing synthesis...so for that, may be there is a demo in which you can get the design and also readme file in which you get the scripts and other details.
Just go through the documents which is provided in the tool directory itself...so from that you get the path for the library..or you need to find/grep from the directory.
 

well the RTL code is written by you.
the IPs (std cell, memories...) could be develope by you or bought to a IP providers.
 

I can write rtl code, but i want big design and don't want to give too much time in designing.
Thats why I am asking if you have any link from where i can get netlist or verilog modules.
 

you could find some RTL code like LEON processor in opencore.org.
 
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