gnoble29
Member level 1
I have written the following verilog codes.....The first one will execute in one clock cycle......But due to multiple assignments of variable ,the second code is not executing in one clock cycle.....Can anyone suggest any method so that the second code also will execute fully in one clock cycle????
PLZ HELP
//pgrm 1
always @(posedge clk)
begin
s<=8'h01;
s_rot <= 8'h01;
s_2<= 8'h03;
s_out1<= 8'h01;
s_out2<=8'h01;
end
//pgrm 2
always @(posedge clk)
begin
s<=(DATA_WIDTH-m);
s_rot <= s<<1;
s_2<=s+8'h03;
s_out1<=s_rot+8'h01;
s_out2<=s_rot+s_2;
end
PLZ HELP
//pgrm 1
always @(posedge clk)
begin
s<=8'h01;
s_rot <= 8'h01;
s_2<= 8'h03;
s_out1<= 8'h01;
s_out2<=8'h01;
end
//pgrm 2
always @(posedge clk)
begin
s<=(DATA_WIDTH-m);
s_rot <= s<<1;
s_2<=s+8'h03;
s_out1<=s_rot+8'h01;
s_out2<=s_rot+s_2;
end