ecess loop dalay in delta sigma modulators

Hello everyone !!!!

can anyone tell me why the problem of excess loop delay is encountered only in continuous time delta sigma modulators, and not in discrete time modulators ???? (DAC is present in the feedback path in both the cases)

Excess loop delay (ELD) is mainly a problem in CT DSMs because the loop filter is constantly processing CT signals. If compensation for ELD is omitted, its like having a filter with coefficients designed for say a 3rd order loop filter look like a 4th order loop and thus becomes unstable if those coefficients are designed aggressive. Additionally, ELD is used to restore the signal swings within the loop to there original internal swings which again, if swings become to large, the loop filter saturates and instability occurs. Please note, it is possible to design a CT DSM with no ELD compensation, you just have to adjust the coefficients within the loop filter to tolerate this effect, but mainly this is not done because its a good idea to provide say 50% ELD and compensate for it to have sufficient time for the quantizer to make a decision.

In DT DSM, since switch cap is used, this results in the transfer of charge per cycle, thus if you have a longer time, ELD, it doesn't matter because your DT signal should have settled anyways. If they haven't settled, then you need to design for this effect, since not settling will produce a loss in performance. Of course in DT DSMs you do have to look at how the clocking is applied because you need to avoid having to many integrators having full delays instead of half delays.

Hope this helps,

JGK