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[Moved] about overflow problem in vhdl programming

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kannan2590

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if i am having 8 bit input signal and 20 bit coefficient ,so the output will be 28 bit,so my question is if overflow occurs at the output then how to solve the problem and get the correct desired output
 

I assume you are talking about unsigned multiplication. If you are, then you'll never get overflow under the stated conditions.
 

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