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Channels length of a device gets shorter and shorter. At the same time, maximum allowed drain source voltage is scaled, but not at the same pace. Thus the internal electric field on the drain side increases, raising the risk of carrier such a high speed (get 'hot') that they may enter the gate oxide.
One uses drain engineering of the MOS devices to reduce the filed. One typical example is the LDD structure (lightly doped drain) which adds a small lower doped part to the drain of the transistor. The space charge region there may extend a little bit more, thus reducing the field.
You solve HCE by things like lightly doped drains, and of
course respecting the discovered voltage limits from your
reliability characterization. You improve it by the qualities
of your gate, spacer, trench/locos oxides (their trapping
characteristics).
One pernicious dynamic in the industry, is that foundries
and fabless outfits like to take advantage of any assumption
they can, to push the fields (hence performance) higher -
they will assume "use models" for a digital process which
an analog application could never stand, if it was biased
continuously at/near peak substrate current (not that
unreasonable, for some topologies - like a regulator at
the wrong load-point); they will assume a limited low
temperature minimum which your industrial design will
violate (cryo, forget it). And they'll assume a shorter
consumer-product life cycle than perhaps some of you
are tasked to meet, by -your- customer.
And these assumptions may appear only in internal docs
to which you are not privy, or must aggressively extract
from them with the help of whoever's writing the check.
Hi,
From design point of view, if one wants to use LV device for HV supply operations.
On has to use cascading, or extended drain structures for reliability.
One should run GOX or SOA sims before putting such design onto production.
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