Cadence not including effect of substrate contact in DC operating point

Hello Forum (1st post),

I want to observe the effect on operating point and RF performance when the source of a cascoded RF NFET is connected to its bulk in a p-sub IBM 0.13um CMOS process (design mistake). I am working in Cadence. This concern is with regards to the standard RF NFET (not triple well), so the bulk of the NFET is not isolated from the substrate. Thus, having a source voltage above the ground potential should cause current to be drawn into the substrate. I was under the impression that the RF FET model would include the effect of the substrate contact in solving the DC operating point. I have observed that this is not the case at all in my schematic level and extracted simulations. Is there some kind of switch in the FET model that I need to have enabled in order to account for this?

Note: I have attached a substrate connection symbol/cell (subc) to the source of the cascode in the schematic in order to simulate the effects of the substrate contact (with the appropriate dimensions/resistance), but I am not sure if this is going to provide accurate results...

Thanks,

Richard

So, what happens when the source/bulk of the NMOS transistor is biased positively?
Will the bulk/body voltage rise, due to a current injection (majority carriers - holes) into the substrate, that will be picked up (extracted from the substrate) by the neighboring p+ contacts / guard rings?
Do you want to account for that body voltage increase in your circuit simulation?

If no - please explain the physics of what will going on.

If yes - I don't think it's reasonable to expect that the compact models would account for the layout and substrate R/RC parasitic effects - unless you use some dedicated tool / flow.

Hand waiving description of these effects is simple, but simulating these effects with a reasonable or acceptable accuracy is a huge challenge.