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VHDL read/write keywords

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shaiko

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COMPONENT some_component is
PORT
(
Read : OUT std_logic ;
Write : OUT std_logic ;
);
END COMPONENT;
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What is the purpose of "read" and "write" keywords is VHDL ?
How are they used ?
 

So what is their purpose ?
 

in your code, they are just single bit outputs of the component.
 

They're not keywords, they're port names. If you don't know that one I'm afraid you won't get vhdl.
 

hey,

I think you are regerring to READ and WRITE from TEXTIO package. If that is the case then they are used to read/write anything from/into any file (say txt file) in your hard-disk. Refer to std_logic_textio.all. Link is https://www.csee.umbc.edu/portal/help/VHDL/textio.vhdl.

However, in your code they are simple OUT ports.

Abhishek
 
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    shaiko

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READ and WRITE are actually implied for all file type, along with the ENDFILE function, in theory allowing you to read any type from any file. The textio package (std_logic_textio only declares them for std_logic/std_logic_vector) declares new versions allowing you to read and write strings to text files, and should work as intended (the implied READ and WRITE may not work the same with all simulators annoyingly).
 

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