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About MOS gate fringer number and BW

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rats

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fringer number of mos

I am designing a Limiting Amp, process is ST0.13um, when W/L=23/0.13, the BW is about 3GHz, but if gate fringer number >1, the BW is larger with peaking. As I knew using fringer configuration can reduce the Capacitance of Gate, becasue of the areas shared, But what induce peaking?
Is there any theory to explain this? Thank you in advance.
 

I think there is a possibilities that since your gate capacitance is reduced, the GBW is larger while possible that the second pole does not increase correspondingly, thus reducing phase margin and cause peaking.
 

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