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PMOS is ON when its Gate voltage goes negative wrt source.
it is true for PMOs.
but your second part
...
still why do we say that pmos is ON if a zero is applied at the GATE?...
is not clearly specified, i think..
It is in fact not the gate voltage but the gate-source voltage. In 90nm, your supply is perhaps 1.2v, In the inverter case, the pmos source is connected to the supply. If gate is also connected to the supply, then you don't attract any holes to form the channel because Vgs=0. Start lowering gate towards 0V. When gate goes about 0.35V below source (Vg=0.85V), or gate is negative with respect to source or Vgs=-0.35V then you have certain amount of holes already attracted under the gate and the transistor is just about to start conducting. If you lower gate voltage even further, the channel becomes "fatter" and the transistor conducts stronger. If the drain of the pmos is connected to the drain of an nmos which is turning off at the same time like in the inverter, then the stronger you turn on the pmos, the weaker the nmos becomes - in other words pmos wants to conduct current but nmos opposes it. When nmos is off, the pmo current cannot flow anymore and the only possibility is for the drain of the pmos to become equal to the pmos source voltage, because current is 0 for Vds=0.
If you're doing circuits, I recommend that you learn device physics well, but then keep it at the back of your mind while you only use the concepts of current, voltage and charge to analyse the circuit operation. If for every circuit you start thinking in terms of holes and electrons, things become very complicated and this is not an useful approach.