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Flipflops realised in FSM --- HDL Coding

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graphene

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Hi all,

I am using a FSM and few other sequential and combinational blocks along with it. My logic in top level would automatically realise me a flipflop (2 inputs mux'd and wired thru a D-FF to one of the input of the FSM). I have tried all possible input combinations but many a times the DFF just gives a Logic-X irrespective of both the inputs having a logical 1 or 0 . The transient from x to the value intended doesnt happen as the DFF remains in the state X. Can anyone please help me ?

Thank you all in advance !!
 

Are you using VHDL or verilog to code this?. Make sure, clock should in sensitivity list for FSM coded designs.
 

Hi Sam.. I am using Verilog. I am able to work logically and simulate it in Modelsim but at the netlist level it doesnt. Also YES the clock in in the sensitivity list in my FSM, other blocks where its needed. Any more info can I share with you ?
 

Got it. You dont see any issue in RTL simulations , where as netlist simulations are having X.

Can you check these things?.

1. Is timing closed for this block.
2. check the timing reports for the corners , you are running simulations and make sure you dont have any Setup and hold violations.
3. Are you running the same clock frequency, where STA is closed?.
4. To make sure, timing is not a problem, run the netlist simulations with 1Mhz.
5. Do you see any SDF related errors/warnings in the log report. Is there any annotation issues?.

Regards,
Sam
 

I think I got a break thru with your suggestions... will check and let you know ASAP .. many man thanks to u..
 

hi Sam,

I happened to check and found that the timing is not closed, dint change the freq for the STA... i got some warnings which I feel dint match to this.. Anyways one more task u mentioend regarding the change of frequency is yet to b done. will do that asap. thank u once again. I learnt/am learning thru this 'n u a lot..
 

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