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generating a since LFO in VHDL

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juggler

juggler

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generating a sine LFO in VHDL

I want to be able to modulate a parameter in my audio processing project using a some kind of variable sine LFO in VHDL.

Whats the best way to go about this? It only needs to vary from say 0-20hz and it has to be offset to make the whole thing positive since its value will actually be a pointer.

Suggestions?
cheers
 
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A DDS generator seems just perfect for this purpose. Offsetting the normally bipolar output range to unipolar is a simple thing.
 

Thanks for the reply, would a DDS require some form of look up table? obviously this wouldnt require a high resolution at all. Are there any working examples around?
 

Besides the said IP blocks of major FPGA vendors, you'll find many code examples at edaboard. I know, that I posted at least one, demonstrating sine table generation in VHDL.

Yes, look-up table (LUT) is the straightforward way, there are also other generation algorithms, particularly interesting for high resolution sine. I guess, that 8 or 10 bit (both magnitude and phase resolution) are sufficient for your application, suggesting a small ROM table.
 

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