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Fixed-point division in VHDL

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Hi everybody, i'm quite new to vhdl and hardware implementation and i have a problem.
I have to implement a weighted average (weights are not constant) with integer fixed-point numbers. The problem is that the sum of the weights (the divisor in the average) is not always a power of 2, so how i can perform that division WITHOUT use any ipcore divider?
The approximation of the divisor to the nearest power of 2 is not always a good choiche because the result could be not accurated enough.
Thank you in advance

ps: i use xilinx ise 13.2
 
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If the weight factors are constants, you would want to refer to a multiplication. Scaling the factors for a sum of 2^N would be another option.
 
Unfortunately weights are not constants :s
 

O.K., than use any divider of your choice. A serial divider would be preferred for lower resource requirement.
 

How do you exactly qualify an "IP core divider"?Explicitely instantiated vendor libraries? Vendor libraries inferred from operators like "/"? Any third party components used in your code? Component code copied from a text book?
 

i'm a newbie, so i suppose "Explicitely instantiated vendor libraries" , in my case xilinx core generator.
 

I looked for some algorithms, there are two class: "subtractive alg"(slower) and "multiplicative alg"(faster).
I have a question for the multiplicative class : the newton-raphson and series expansion methods aims to calculate the reciprocal of the divisor, then multiply it for the dividend. but these methods works only if divisor < 1 ; in my problem the divisor is never < 1.
My opinion is: this should not matter as std_logic_vector bits remain the same, but change the representation/interpretetion [ "110000000" can be either 384 fixed point(9,0) or 0.75 fixed point(0,9) ] , so i suppose that the algorithm works. Is this correct?
 

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