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modelsim error when simulating an asynchronous fsm

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shaiko

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Below is a VHDL code for an asynchronous state machine :

Code:
asynchronous_fsm : process 
(
	reset ,
	address ,
	data ,
	general_register_1 ,
	general_register_2 ,
	event_register ,
	mask_register ,
	events ,
	dsp_on ,
	state ,
	any_event_detected ,
	unmasked_event_detected
) is
begin

	if reset = '0' then 
		
		dsp_on <= '0' ; 
		general_register <= ( others => '0' ) ;	 	 	
		mask_register <= ( others => '0' ) ;	
		event_register <= ( others => '0' ) ;		
		fsm_state <= fsm_idle_state_0 ;
		
	else

		case state is
		
			when idle_state =>
						
				if any_event_detected = '1' then
					event_register <= events ;
					if unmasked_event_detected = '1' then
						state <= on_state ;	
						dsp_on <= '1' ;
					end if ;	
				end if ;		
				
			
			
			when on_state =>
			
				if general_register_1 ( 0 ) = '0' then 						
					dsp_on <= '0' ;	
					state <= idle_state ;	
				end if ;						
				if address = mask_register then 
					mask_register <= data ;						
				elsif address = general_register_1_address then
					general_register_1 <= data ;
				elsif address = general_register_2_address then
					general_register_2 <= data ;					
				end if ;						
				
		end case ;
		
	end if ;
	
end process asynchronous_fsm ;

When I try to simulate the above with modelsim I get the following error:
Error: Iteration limit reached at time 1 ns.

What should I do in order to make the code simulatable ?
 

clearly, something has got into an infinite loop
You can use the tools in modelsim to try and trace it

---------- Post added at 08:30 ---------- Previous post was at 08:30 ----------

clearly, something has got into an infinite loop
You can use the tools in modelsim to try and trace it
 
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    shaiko

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When you go to on_state and general_register_1 ( 0 ) = '0' you have an oscillator, since it will go back to idle_state immediately.

If state is represented by more than one bit you will have another problem in the real circuit but not in simulation.
You can not assume that all bits toggle at the same time, so you can have short "glitches" of other states, and that can of course have bad effect on an asynchronous state machine.

There are reasons why designers don't do what you are trying to do. The tools don't help you much and with a larger design you will never find all the bugs.
The design can simulate perfectly but fail when the synthesized circuit is used in a real FPGA.
 
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    shaiko

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