TuAtAu
Advanced Member level 4
Hi all,
I am designing a IP CORE/Soft Microprocessor, ARM based, RISC, 5 stage PIPELINE, CACHE, DSP, ALU, HAZARD CONTROLLER etc.
Currently using Xilinx xc3s1200, after Implementation, it say maximum available frequency is only 20MHz.
I wish it to reach 100MHz!
What is the problem? What actually limit the clock?
any idea?
I am designing a IP CORE/Soft Microprocessor, ARM based, RISC, 5 stage PIPELINE, CACHE, DSP, ALU, HAZARD CONTROLLER etc.
Currently using Xilinx xc3s1200, after Implementation, it say maximum available frequency is only 20MHz.
I wish it to reach 100MHz!
What is the problem? What actually limit the clock?
any idea?