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problem with vhdl code- don't understand the wrong

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shaolomc32

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I write a simple code for changing the velocity of dc motor.
the code check the velocity and change the pwm value.
but the compilation of the program is not successful.I get an error massege and don't know the meaning.
please your answer.
here is the code and the wrong massage :
the code :



Code: 
library ieee;
use ieee.std_logic_1164.all;
entity TEST_MASHOV is
port(clk,rst  : in bit;
	  r,c : in integer range 0 to 255;
		pwm_out : buffer integer range 0 to 255);
end;
architecture behave of TEST_MASHOV is
type st is (go,medida,lit_slower,big_slower,lit_faster,big_faster);
signal state :st;
--signal cc,ccc:integer range 0 to 255;
begin
--cc<=c;--(c*2)+10;
process(clk,rst)
begin
if rst='1' then state<=go;
elsif clk'event and clk = '1' then
case state is
when go => pwm_out<=100; state<=medida;
when medida => if  r<c then state<=lit_slower;
               elsif c>(r+15) then state <=big_slower;
			   elsif r>c then   state<=lit_faster;
               elsif r>(c+15) then state <=big_faster;
			  end if;
when lit_slower => if pwm_out>90 then pwm_out<=pwm_out-2; state<=medida; else state<=medida; end if;
when big_slower=> if pwm_out>90 then pwm_out<=pwm_out-10; state<=medida; else state<=medida; end if;


when lit_faster =>  if pwm_out<255 then pwm_out<=pwm_out+2;  state<=medida; else pwm_out<=255;  state<=medida; end if;
when big_faster =>  if pwm_out<255 then pwm_out<=pwm_out+10;  state<=medida; else pwm_out<=255;  state<=medida; end if;

end case;
  
      end if;
      end process;
end behave;


and the wrong massage is :

unknown problem in test_mashov.vhd
internal error:"width mismatch in relation operator" in eBuildBinaryOp at 1347 of file readxpr.c.


if anyone can help ,I will thank to you .
 
Last edited by a moderator:

Take a look at your signal definitions.

May be some of the accepting signals aren't at the same width as the driving signals.
It's not allowed in VHDL.

For example:
If signal 'a' is defined as a vector(7 downto 0) and signal be is defined as (6 downto 0). You cannot write:
a <= b;

Try changing your code from integers to vectors. It'll be easier to debug your problem
 

shaiko said:
Take a look at your signal definitions.

May be some of the accepting signals aren't at the same width as the driving signals.
It's not allowed in VHDL.

For example:
If signal 'a' is defined as a vector(7 downto 0) and signal be is defined as (6 downto 0). You cannot write:
a <= b;

Try changing your code from integers to vectors. It'll be easier to debug your problem
Click to expand...

tank you/
I will try it
 

It could be that pwm_out becomes bigger than 255 and thus fall out of the range of 8 bit.
But like TrickyDicky wrote, the line indication is line 1347. You should have a look at that line.
 

I don't have this line number: 1347. the code is only by almost 30 lines.
secondly-the maximum high sped of pwm in my project is 255 rpm so this is not the wrong,I gess.
 

secondly-the maximum high sped of pwm in my project is 255 rpm so this is not the wrong,I gess.
Click to expand...

Well maybe it is the problem :
Code: 
when big_faster =>
   if pwm_out<255 then
      pwm_out<=pwm_out+10;
      state<=medida;
   else
      pwm_out<=255;
      state<=medida;
   end if;
Look at this piece of code:
when pwm_out is 254 (in the range of the if switch), so 10 will be added to pwm_out, thus 264. This is not in the range of 8 bit (and out of the intended 0 to 255)

by the way - the error refers to readxpr.c (!)
 

An internal error is usually referring to a tool bug, even if it's triggerred by a VHDL syntax errors, which isn't the case here.

What's your tool?

when pwm_out is 254 (in the range of the if switch), so 10 will be added to pwm_out, thus 264.
Click to expand...
Two comments.

A synthesis tool will usually infer unsigned(7 downto 0) from integer range 0 to 255, so the discussed range violation will be handled by a simple overflow.

A simulator like Modelsim will in contrast raise a simulation error, if the actual value causes a range violation.
 

I will try to fix it.maybe the problem is this.
thanks a lot

---------- Post added at 11:53 ---------- Previous post was at 11:35 ----------

I try all the sokutions that all of you suggessted.it didn't work!!
the last change in code done about the kind of vriable and this is the wrong massage I recieved :
line 22: subprogram error : can't interpretsubprogram call
line 24 : subprogram error : can't interpretsubprogram call

the changes is the new code are marked .the piece of code:






r,c : in bit_vector(7 downto 0);
pwm_out : buffer integer range 0 to 255);


when lit_faster => if pwm_out<240 then pwm_out<=pwm_out+2; state<=medida; else pwm_out<=255; state<=medida; end if;
when big_faster => if pwm_out<240 then pwm_out<=pwm_out+10; state<=medida; else pwm_out<=255; state<=medida; end if;

end case;
 

Now it's turning to trivial VHDL syntax errors. You can't perform arithmetics with bit vectors.
 

hi
I try to understand your question "what tool I'm using"?
what do you mean to?
if its about the kind of chip so I use in CPLD chip in Development Kit of UP2.
I use in Max plussII software.
 

max plus 2 is very old software and it's VHDL support is pretty poor. (about 10 years old now!)
I suggest upgrading to quartus and modelsim.
 

the situation now is that I worked with Max-Pluss .
 

thanks a lot about the all answers for trying help me
 

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