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Reading input in vhdl

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ghostridergr

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Hello! i want to read input from a file, and i have written a testbench which is correct for reading positive integer numbers.
But when i read negative numbers it gives me error message so its either problem of my reading input or of my vhdl programme.

What i want is when reading a negative number "tranform" it in the following form: msb is the sign (1 for negatives) and the rest bits is the numbers.
can anyone help me with the readline and read functions? how do they behave when reading negative integers?

Thanks!
 

it sounds like you are reading these in as binary? how about reading them in as integers? its perfectly possible to read these from a text file:

10
11
-111
-99
--etc

and from this you can convert it to any type you like. But the number format you are talking about - what you describe is almost 2s compliment - is that what you mean. Or do you need a special format where the MSB is the sign and the rest is an unsigned version of the number. if so, why not 2s compliment, as that is the standard used by everything.

What code have you got so far? how are your input files formatted?
 

TrickyDicky said:
it sounds like you are reading these in as binary? how about reading them in as integers? its perfectly possible to read these from a text file:

10
11
-111
-99
--etc

and from this you can convert it to any type you like. But the number format you are talking about - what you describe is almost 2s compliment - is that what you mean. Or do you need a special format where the MSB is the sign and the rest is an unsigned version of the number. if so, why not 2s compliment, as that is the standard used by everything.

What code have you got so far? how are your input files formatted?
Click to expand...
yes i am reading it as integer, and i want the 2nd format you mentioned: MSB to be the sign, and the rest to be the unsigned version of the number. i will post my code later as i am making some changes. So if i read the number -5 for example i want the msb to be 1, and the rest to be 101.

the function read that i am using will give me what i want or it will give me the 2's compliment?
 

Well all integers are stored 2's compliment (because it allows you to do arithmatic with just adders). Without 2s compliment the logic gets much more complicated.

For non-2s compliment you will need to write custom conversion functions.
Any particular reason you want non-2s compliment?
 

its ok i just changed the rest of my code, and used 2's compliment instead. It was much more easier as you said. Thanks!
 

I agree, that using 2s complement throughout the design is the most simple way. Conversion between 2s complement and sign-magnitude is however simple, just a conditional negation of negative numbers after copying the bit vector, and restore the sign bit afterwards.
 
ok now i want to turn my negative number in its abs, and i am using the following:

Code: 
to_be_squared<=abs(conv_integer(signed(temp_out_dif)));
where temp_out_diff is of type std_logic_vector.. it doesn't work either with the type cast, either without it.. i have included the following packages

Code: 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

and this is my error message:

Code: 
type error resolving prefix expression abs as type " IEEE.std_logic_1164.STD_LOGIC_VECTOR"


---------- Post added at 01:24 ---------- Previous post was at 00:59 ----------

Problem solved

ghostridergr said:
ok now i want to turn my negative number in its abs, and i am using the following:

Code: 
to_be_squared<=abs(conv_integer(signed(temp_out_dif)));
where temp_out_diff is of type std_logic_vector.. It doesn't work either with the type cast, either without it.. I have included the following packages

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

and this is my error message:

Code: 
type error resolving prefix expression abs as type " ieee.std_logic_1164.std_logic_vector"
Click to expand...
 

I would recommened ditching the non standard std_logic_arith and std_logic_unsigned/signed libraries. Use the IEEE standard numeric_std instead.

Also, you shouldnt be using std_logic_vectors for numbers, even on ports. use signed/unsigned (from numeric_std, not std_logic_arith) instead.
 

can anyone help me with that... if my read function reads from my input file the number -0,000234 what it will return?

and secondly wtats the difference of using numeric_std rather than std_logic libraries?

thanks!
 
Last edited:

I would use read() with a real result variable, after changing the text to -0.000234. Then using ieee.math_real to change it into a number format understood by the design under test.
 

numeric_std is a IEEE standard and part of the vhdl language. std_logic_arith/unsigned are not.

to read the real value once you've read it like fvm suggested try using the new fixed point packages.
 

1)ok to conclude, if i want to my read function to return only the -234 (if my initial reading value is -0.000234) what conversion do i have to make?
2)below is my vhd code. the problem is that it doesn't change my reading input (i mean it reads nothing, only the clk changes its value, the a,b inputs have "00000000" as value).
for the moment i read from the file only integer values
Code: 
library IEEE;
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;


entity tb_file_square_dif is
  generic
		(
			N :integer := 8
		);
end tb_file_square_dif;


architecture TB_ARCHITECTURE of tb_file_square_dif is
file IN_VECTORS: TEXT open READ_MODE is "input.txt";
file OUT_VECTORS: TEXT open WRITE_MODE is "output.txt";
--here
component squaredif_n
    port(
        a,b: in signed(N-1 downto 0);
        bin: in std_logic;
        clk:in std_logic;
        d: out signed(2*N-1 downto 0);
        bout: out std_logic);
end component;
signal a,b: signed(N-1 downto 0);
signal bin,clk: std_logic;
signal d:signed(2*N-1 downto 0);
signal bout: std_logic;
begin
    UUT: squaredif_n
        port map (
          a=>a,
          b=>b,
          bin=>bin,
          clk=>clk,
          d=>d,
          bout=>bout);
            
    process
        variable IN_BUF: LINE;
        variable OUT_BUF: LINE;
        variable clk_var,bin_var,bout_var : bit;
        variable a_var,b_var : bit_vector(N-1 downto 0);
        variable dout_var:bit_vector(2*N-1 downto 0);
    begin
        while not ENDFILE(IN_VECTORS) loop
            READLINE(IN_VECTORS,IN_BUF);
            READ(IN_BUF,a_var);
            READ(IN_BUF,b_var);
        bin<='0';
        read_inp: for k in 0 to N-1 loop
              a(k)<=to_stdulogic(a_var(k));
              b(k)<=to_stdulogic(b_var(k));
        end loop;
            wait for 1 ms;
            WRITE(OUT_BUF,STRING'("SQUARE DIFFERENCE IS= "));
            WRITE(OUT_BUF,conv_integer(d));
            WRITELINE(OUT_VECTORS,OUT_BUF);
        end loop;
        wait;
    end process;
    
  process
  begin
     clk<='0';
     wait for 10 ns;
     clk<='1';
     wait for 10 ns;
  end process;
end TB_ARCHITECTURE;
 
Last edited:

can you provide the input file?

---------- Post added at 10:24 ---------- Previous post was at 10:22 ----------
1)ok to conclude, if i want to my read function to return only the -234 (if my initial reading value is -0.000234) what conversion do i have to make?
Click to expand...

This isnt a conversion. You can read in -0.000234 via a real type. to get it to -234 just multiply it by 1000.
 

For legacy std_logic_arith library, the conversion can look like
Code: 
variable a_real: real;
...
read (in_buf,a_real);
a <= conv_unsigned(integer(a_real*1.0**6),N);
You also need something like wait until rising_edge(clk) to synchronize the file processing with the datapath of the design under test.
 

TrickyDicky said:
can you provide the input file?
Click to expand...
it's just a file with binary values.

for example it has those values:
111 100
01 110
11 1

what i see is only my clk signal changing and my a,b signal stay in "0000000" and my d(output) to UNDEFINED. also i put int the while loop write statements and it doesn't print anything. can anyone help me with that and suggest me what to do cause i am so confused and it is of crusial importance to understand how to test my vhdl programme using an input file.
 

If those are the values in the file, the problem is there are not enough bits in them.
According to your code, you're trying to read in 8 bit values. But the values seem to vary in length.
Each value in the text file has to be the same number of bits as the bit_vector (or std_logic). Integers dont matter so much because you can read in what you want.

If the values are not long enough, the read will fail (hence you always having 00000) If you used std_logic_vector, you would have "UUUUUUUU" telling you there is a read problem
 

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