[SOLVED] Vrefp and Vrefm in DT Sigma delta ADC. What is the best way to make these voltages?

Hello all,

I am working on a DT sigma delta ADC and I am having trouble producing the Vrefp and Vrefm used to feedback my quantizer result. The question is...What is the best way to make these voltages. Just use the same resistive ladder in my quantizer but blow alot of current to provide a solid Vrefp and Vrefm? Then just add on a cap to filter any of the high switch noise? Or should I use high speed buffers off of a low current resistive ladder?

How do people commonly makes these voltages?

I would think the high current ladder would be my best bet because having two high speed buffers would consume alot of power.....Any other ideas???

Jgk

We successfully used 2 buffers with ½µA of quiescent current, each (Rout≈2kΩ), and a few tenths of pF's at the ref inputs (filling otherwise unused space). Low current was more important than real estate consumption.

BTW: the still existent mV spikes on the Vrefs didn't do any harm. It was an RSD ADC, however, where ref accuracy isn't that important.

erikl said:

We successfully used 2 buffers with ½µA of quiescent current, each (Rout≈2kΩ), and a few tenths of pF's at the ref inputs (filling otherwise unused space). Low current was more important than real estate consumption.

BTW: the still existent mV spikes on the Vrefs didn't do any harm. It was an RSD ADC, however, where ref accuracy isn't that important.

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Just wondering but what was your clk frequency. I am operating at 1GHz and my LSB is 50mV. I do agree I can handle anything around ..10mV ripple without effecting my ADC, but what you are saying is a dream.... a few uAs... Right now without losing anything in performance i need about 1mA of current in my ladder which is a ladder with 50ohm links.. Is it more common do design with these buffers then the ladder.... I think I wouldn't mind just wasting the space on caps to filter the Vrefs....

Is there any other alternative?

Also what is a RSD ADC.... RSD=??

Jgk

jgk2004 said:

Just wondering but what was your clk frequency. I am operating at 1GHz and my LSB is 50mV.

Click to expand...

Just a Mhz, a real slow one, but LSB < 1mV . 11bit reso , ENOB ~10bit.

jgk2004 said:

a dream.... a few uAs...

Click to expand...

For a Vref buffer enough, with some additional C

jgk2004 said:

Also what is a RSD ADC.... RSD=??

Click to expand...

Redundant Signed Digit, 1½ bit per comparison, hence Vref and comparator accuracy isn't a big problem.

Ok then it all makes sense, since I am at a CLK of 1GHz, then I would expect 500uA per buffer in comparing to your structure, or 1mA in the ladder.. Thanks for the feedback

Are there any other ideas?


Jgk

jgk2004 said:

... I would expect 500uA per buffer in comparing to your structure, or 1mA in the ladder.. Jgk

Click to expand...

Hi John,

with 1mA in the ladder you get a drive impedance in the order of ~1kΩ, i.e. you can load a cap of -- say -- 100fF in a few 100ps , working with a 1GHz clock, however, you should load it a bit faster in order to leave enough time for the real work (I presume you have to switch the reference voltages). With a 10µA (consumption) buffer you can achieve an output resistance in the order of 100Ω , i.e. a load time constant of ~10ps.

Of course you have to trade speed & lower power consumption against real estate.

Regards, erikl