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[SOLVED] Trouble with ModelSim, trying to use std_logic_textio synopsys hread procedure

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Trouble with ModelSim, trying to use "std_logic_textio" synopsys "hread" procedure

I'm trying to use the hread procedure from std_logic_textio.vhd from synopsys in ModelSim and I'm running into some trouble. Currently my vhdl testbench throws an error during compilation saying: "Unknown identifier "hread".

Here's what I have done:

1. I've added std_logic_textio.vhd to the Project in ModelSim from C:\modeltech_6.5c\vhdl_src\synopsys
2. Added library work; and use work.all; to VHDL testbench header (I think this is necessary?)
3. have a .do file that does:
project compileoutofdate
vcom -refresh
vsim -novopt work.tb_name -t 1ps
do Waveform.do

and then get an error: "Unknown identifier "hread"" ....... when doing this: hread(my_file, my_slv_v);

Anyone have any ideas as to what the problem might be? I'm quite stuck.
 

thats not how it works.
std_logic_textio is part of the ieee library, so in your code you just add the lines:

library ieee;
use ieee.std_logic_textio.all;

secondly, if you did compile it into work, you would not add work.all; it would be work.std_logic_textio.all;

Then you have access to hread. Including it in work means you wont get the accelerated versions of the procedures (as modelsim has these pre-compiled).
 
TrickyDicky,

I tried your suggestion with no luck :???:

I'm using hread on some dummy code now and ModelSim throws an error saying: "No Feasible entries for subprogram "hread"."

I must be doing something wrong still, I've attached screenshots and code for reference.

I got the Synopsys std_logic_textio.vhd from here:
http://www.eda.org/rassp/vhdl/models/standards/std_logic_textio.vhd

Here's the code: (the hread part is down near the bottom)
Code: 
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use work.std_logic_textio.all;
use std.textio.all;

entity two_bit_comp_tb is
end two_bit_comp_tb;

architecture tb_arch of two_bit_comp_tb is
  type intfile is file of integer;
  file hexfile : intfile;
	signal test_in0, test_in1: std_logic_vector(1 downto 0);
	signal test_out: std_logic;
	signal test_i32_in0, test_i32_in1: integer;
	signal test_i32_out0, test_i32_out1: integer;
begin

-- instantiate the circuit under test
	uut: entity work.two_bit_comp(arch)
	 port map(a => test_in0, b => test_in1, aeqb => test_out, 
	          u32_in0 => test_i32_in0, 
	          u32_in1 => test_i32_in1,
	          u32_out0 => test_i32_out0,
	          u32_out1 => test_i32_out1);
-- test vector generate
stimulus: process
  variable test_iv32_in0: integer;  --unsigned(31 downto 0)
  variable test_iv32_in1: integer;  --unsigned(31 downto 0)
  variable slv_32_in: std_logic_vector(31 downto 0);
begin
	-- test vector 1
	test_in0 <= "00";
	test_in1 <= "00";
	wait for 200 ns;
	-- test vector 2
	test_in0 <= "01";
	test_in1 <= "00";
	wait for 200 ns;
	-- test vector 3
	test_in0 <= "01";
	test_in1 <= "11";
	wait for 200 ns;
	-- test vector 4
	test_in0 <= "10";
	test_in1 <= "10";
	wait for 200 ns;
	-- test vector 5
	test_in0 <= "10";
	test_in1 <= "00";
	wait for 200 ns;
	-- test vector 6
	test_in0 <= "11";
	test_in1 <= "11";
	wait for 200 ns;
	-- test vector 7
	test_in0 <= "11";
	test_in1 <= "01";
	wait for 200 ns;
	-- test vector 8
	--without HREAD
	file_open(hexfile,"C:\Users\Owner\Desktop\two_bit_comp\hex_data.txt",read_mode);
	read(hexfile, test_iv32_in0);
	report (integer'image(test_iv32_in0));
	test_i32_in0 <= test_iv32_in0;
	read(hexfile, test_iv32_in1);
	report (integer'image(test_iv32_in1));
	test_i32_in1 <= test_iv32_in1;
	file_close(hexfile);
	--with HREAD  **HERE'S WHERE THE PROBLEM IS**
	file_open(hexfile,"C:\Users\Owner\Desktop\two_bit_comp\hex_data.txt",read_mode);
  hread(hexfile, slv_32_in);
	file_close(hexfile);
	-- terminate simulation
	assert false
		report "Simulation Completed"
		severity failure;
	end process;
end tb_arch;
 

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  • ModelSim HREAD Error.png
    ModelSim HREAD Error.png
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  • ModelSim Project Files.png
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First of all, stop using a downloaded copy of std_logic_textio. It will make matters worse. Delete the work.std_logic_textio reference in your code.

Secondly, if you declare afile of type integer, you can only ever read integers from the file, not anything else. The textio package defines a type called text that is used in all the textio packages and allows you to read in many types, not just integers. hread is only compatable with text files, not integer files. Then you also need a line type variable that allows you to read in data from text files.

so you need code that looks like this:
Code: 
process
  file infile : text open read_mode is "some_file.txt";
  variable inline : line;
begin
  
  .....
  FILE_OPEN(infile, "some_file.txt" ) --if you didnt open it at the declaration, like above.
  readline(infile, inline);

  hread(inline, my_slv);  --hread only works with lines, not files
end proces;

I suggest you find a textio tutorial and get reading.
 
Last edited:
Ok thanks you're the man, I'll try this out now. I've looked through a number of examples online where people used textio and all the explanations seemed to be piecemealed together, it was hard to get a firm grasp of what the heck I was doing. I'll see if I can find some better ones.
 

It's working. :smile:

I've been reading some tutorials and what you're saying makes much more sense.

Thanks again.
 

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