Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Complex numbers in VHDL

Status
Not open for further replies.
R

Richard Divakar Vemagiri

Newbie level 6
Joined
Feb 25, 2011
Messages
14
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,393
Hi,
I'm trying to write an FFT VHDL code and would like to know how i should be dealing with complex numbers in VHDL...
Please help me out..

Thanking You,
Richard Divakar Vemagiri.
 

May be you can specify a record type for a complex number. This record type can contain two fields -one for real part and another for complex part.

Now define and write seperate functions for complex type addition, subtraction,multiplication etc for using it in the FFT code.
Creating a package containing the above type definitions and functions may be an ideal way.
 

Richard Divakar Vemagiri,

You could try this site, it may have what you are looking for. Standard VHDL Packages

I have not had a chance to play with complex math yet, but I am sure the day will come.
Hope that helps some.
Sckoarn
 

the math_complex package is not synthesisable, because it uses real types.
 

Hi,
I want to perform a right shift operation using the 'sra' keyword in VHDL. I have a signed bit vector of size 65 and i need to perform sra operation on it. I wrote as - p sra 1. I'm getting an error when I'm compiling saying:
near "sra": expecting <= or :=
Can you help me out in knowing what to do?

Thank you,
Richard.
 

Richard,
I think the syntax may be more like this:
p <= p sra 1;

Sckoarn
 

Hi Sckoarn,
In my code, 'p' is a variable. So i tried as p:=p sra 1;. Still i am getting the same error - near "sra": expecting <= or :=.
Please let me know how to correct this, if possible.

Thank you.
 

Richard,
It looks like the operation only works on a "bit_vector" type.
bit_vec <= bit_vec sra 8;
I got the above line to compile. But using std_logic_vector did not work. You can convert to bit_vector in a simple loop.

Hope that solves your problem.
Sckoarn
 

Hi Sckoarn,
Thanks for that help. I'm actually not familiar with the differences among bit_vector, std_logic_vector and signed. Can you just tell me how these three types differ?

Richard.
 

Richard,
type 'bit' can only have a value of '1' or '0'
bit_vector is a vector of type bit.
std_logic can have values '1', '0', 'X', 'Z', 'H', 'L', 'U' ... I think thats all of them
std_logic_vector is a vector of type std_logic.
signed, I think, refers to the left most bit, it is the sign bit in a number.

to convert from a std_logic_vector to a bit_vector a simple for loop: assumes the two vectors are the same size. Also, will convert anything non-zero to zero.

Code: 
for i in (std_logic_vector'high) downto 0 loop
  if(std_logic_vector(i) = '1') then
    bit_vector(i)  :=  '1';
  else
    bit_vector(i)  :=  '0';
  end if;
end loop;
Sckoarn
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top