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bandgap: high temperature leakage compensation

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cmos_ajay

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Hello,
Can someone provide me information about high temperature leakage compensation in a simple bandgap reference ? I will appreciate any diagrams or technical notes for it. Regards.
 

Assume a PMOS current mirror and currents are flowing down into n-p-n BJT's Q1 and Q2<8:1> . There is a resistor R at the emitter of Q2 across which delta_vbe voltage is generated. In a bandgap as the temperature increases, the leakage current in the BJT increases. So the delta(vbe) changes . There is a way to compensate these changes. I had read one reference paper 'Analog cmos integrated circuits for high-temperature operation with leakage current compensation' which gave some information. However, I would like to know "how to size the leakage compensating mosfets" and "how to decide the magnitude of the leakage compensation current that is injected into the BJT's". What test bench do I set up for this ?
 

OK! But it seems to me that the leakage technique explained in “Analog CMOS integrated circuits for High …” is used to compensate the leakage of MOSFETS, and not of BJTs. Do you agree?!
Regards,
 

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