error in synthesis of vhdl code

ERROR:Xst:825 - "F:/hdnew/new test.vhd" line 87: Wait statement in a procedure is not accepted.


i used wait until (t_clk2='1'); in my vhdl code .

Is there any other expression to replace this statement ?

the key point is you have used the wait statement inside a procedure. This is valid VHDL, but only for simulation. It is not allowable for synthesis (as the error has said).

Also, wait until t_clk2 = '1' is not synthesisable. you need:

wait until t_clk2'event and t_clk2 = '1';
or wait until rising_edge(t_clk2);

or even better, put 2_clk2 in the process sensitivity list and use:

if rising_edge(t_clk2) then
...


please post your code so we can inspect further.

begin

unit1: bilbo_system port map (T_CLK2,T_B1,T_B2,T_SI,SO,T_Z,T_Q1);

clk_sig1: process(t_clk2)
begin
T_CLK2 <='1';
T_clk2 <= not t_clk2 after 80 ns ;
--wait for 80 ns;
--T_CLK2 <= '0';
--wait for 80 ns;
--wait;
end process;


mahe rocess
begin
t_B1 <= '0'; t_B2 <= '0'; -- shift in test vector
for i in 0 to 7 loop
t_Si <= test_vector(i);
wait until (t_clk2='1');
--wait for 100 ns;
end loop;

t_B1 <= '0'; t_B2 <= '1'; -- Use PRPG and MISR
for i in 1 to 15 loop
wait until (t_clk2='1');
-- wait for 10 ns;
end loop;



t_B1 <= '1'; t_B2 <= '1'; -- Use PRPG and MISR
for i in 1 to 20 loop
wait until (t_clk2='1');
end loop;
sig <= T_Q1 ;


if (Sig = test_result) then -- Compare signature
report "System passed ";
else
report "System did not test!";
end if;

wait until (t_clk2='1');

end process;

The code you have posted appears to be a test bench. This is not synthesisable. It is meant for testing a unit in simulation.

ERROR:Xst:825 - "F:/hdnew/new test.vhd" line 88: Wait statement in a procedure is not accepted.
-->

---------- Post added at 20:54 ---------- Previous post was at 20:53 ----------

test bench is not necessary for synthesis ?/?

no, only for simulation.

now i m trying to synthesize the UART code than their are lots of warnings ...
is there any effect of it in further processs...?



WARNING:Xst:1293 - FF/Latch <cnt_0> has a constant value of 0 in block <trans>. This FF/Latch will be trimmed during the optimization process.

It means that the latch (cnt_0) doesnt ever change (stuck at 0), and so is redundant. This is then removed by the synthesisor.

actually i m new in this field so i could not understand that how can i remove this ...?

you would have to identify the registers in question and work out why they are stuck at 0.

---------- Post added at 17:44 ---------- Previous post was at 17:42 ----------

This is not always a problem. Sometimes code is deliberatly forced to 0 to force removal of redundant logic. But often is relates to problems elsewhere. Forgetting to connect a clock, holding a reset active or holding an enable inactive are the most common causes of serious logic removal.

if i m ignoring these warnings then go further than i found that their is
No error, but Process "Generate Programming File" failed ..

is any specific reason .

is there any logic in the design?

my project is uart design with bist test pattern ....how can i get the ucf file for it ....

i m sending the code for bist system